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參數(shù)資料
| 型號(hào)： | Pentium II 266 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器) |
| 中文描述： | 32位處理器低功率模塊（帶低能量模塊的32位處理器） |
| 文件頁數(shù)： | 25/50頁 |
| 文件大小： | 1003K |
| 代理商： | PENTIUM II 266 |
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Pentium
II Processor – Low-Power Module
Datasheet
25
4.3.3
PCI Interface
The 443BX Host Bridge/Controller is compliant with the PCI 2.1 specification, which improves
the worst-case PCI bus access latency from earlier PCI specifications. The complete PCI interface
of the 443BX Host Bridge/Controller is available at the connector. The 443BX Host
Bridge/Controller supports the PCI Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain signal when they require the use of the PCI
interface.
The 443BX Host Bridge/Controller is responsible for arbitrating the PCI bus. Since the module is
configured in “mobile compatible” or legacy mode, the 443BX Host Bridge/Controller can support
only up to five PCI bus masters. There are five PCI Request/Grant pairs, REQ[4:0]# and
GNT[4:0]#, available on the connector to the manufacturer’s system electronics.
The PCI interface on the module is 3.3 V only. 5 V PCI devices are not supported, specifically all
devices which drive outputs to a 5 V nominal Voh level.
The 443BX Host Bridge/Controller supports only Mechanism #1 for accessing PCI configuration
space, as detailed in the PCI specification. This implies that signals AD[31:11] are available for
PCI IDSEL signals. However, since the 443BX Host Bridge is always device #0; AD11 will never
be asserted during PCI configuration cycles as an IDSEL. AD12 is reserved by the 443BX for the
AGP bus. Thus, AD13 is the first available address line usable as an IDSEL. AD18 is
recommended to be used by the PIIX4E Southbridge.
4.3.4
AGP Interface
The 443BX Host Bridge/Controller is compliant with the AGP Rev. 1.0 specification, which
supports only an asynchronous AGP interface coupling to the 443BX core frequency. The AGP
interface can reach a theoretical ~500 Mbytes/s transfer rate (i.e., using AGP 2X/133 devices). The
actual bandwidth will be limited by the capability of the 443BX memory subsystem.
4.4
Electrical Requirements
The following section provides information on the DC requirements for the module.
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