參數(shù)資料
型號： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁數(shù)： 14/50頁
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
14
Datasheet
3.1.5
Processor/PIIX4E Sideband (8 Signals)
Table 5
lists the module’s processor and PIIX4E sideband signals at the connector interface. The
voltage level for these signals is determined by V_CPUPU, which is supplied by the module.
PHOLD#
I
PCI
V_3
PCI Hold:
This signal comes from the expansion bridge; it is the
bridge request for PCI.
The 443BX Host Bridge drains the DRAM
write buffers, drains the processor-to-PCI posting buffers, and
acquires the host bus before granting the request via PHLDA#.
This ensures that GAT timing is met for ISA masters.
The PHOLD#
protocol has been modified to include support for passive release.
PHLDA#
O
PCI
V_3
PCI Hold Acknowledge:
This signal is driven by the 443BX Host
Bridge to grant PCI to the expansion bridge.
The PHLDA# protocol
has been modified to include support for passive release.
PAR
I/O
PCI
V_3
Parity:
A single parity bit is provided over AD[31:0] and
C/BE[3:0]#
SERR#
I/O
PCI
V_3
System Error:
The 443BX asserts this signal to indicate an error
condition. Please refer to the Intel 440BX AGPset datasheet
(order number 290633) for further information.
CLKRUN#
I/O D
PCI
V_3
Clock Run:
An open-drain output and also an input.
The 443BX
Host Bridge requests the central resource (PIIX4E) to start or
maintain the PCI clock by asserting CLKRUN#.
The 443BX Host
Bridge three-states CLKRUN# upon deassertion of Reset (since
CLK is running upon deassertion of Reset).
PCI_RST#
I
CMOS
V_3
Reset:
When asserted, this signal asynchronously resets the
443BX Host Bridge.
The PCI signals also three-state, compliant
with PCI Rev 2.1 specifications.
Table 4. PCI Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltage
Description
Table 5. Processor/PIIX4E Sideband Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltage
Description
FERR#
O
CMOS
V_CPUPU
Numeric Coprocessor Error:
This pin functions as a FERR#
signal supporting coprocessor errors. This signal is tied to the
coprocessor error signal on the processor and is driven by the
processor to the PIIX4E.
IGNNE#
I D
CMOS
V_CPUPU
Ignore Error:
This open drain signal is connected to the ignore
error pin on the processor and is driven by the PIIX4E.
INIT#
I D
CMOS
V_CPUPU
Initialization:
INIT# is asserted by the PIIX4E to the processor for
system initialization. This signal is an open drain.
INTR
I D
CMOS
V_CPUPU
Processor Interrupt:
INTR is driven by the PIIX4E to signal the
processor that an interrupt request is pending and needs to be
serviced. This signal is an open drain.
NMI
I D
CMOS
V_CPUPU
Non-Maskable Interrupt:
NMI is used to force a non-maskable
interrupt to the processor.
The PIIX4E ISA bridge generates an
NMI when either SERR# or IOCHK# is asserted, depending on
how the NMI Status and Control Register is programmed. This
signal is an open drain.
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