參數(shù)資料
型號: PEF24901H
英文描述: ?Quad ISDN Echocancellation Circuit Digital Front-End for 4B3T Line Code?
中文描述: ?四整體數(shù)位服務網(wǎng)路Echocancellation電路數(shù)字前端4B3T線路碼的終結?
文件頁數(shù): 60/73頁
文件大?。?/td> 1618K
代理商: PEF24901H
PEB 2466
PEF 2466
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual
51
2001-02-20
8.7
Microcontroller Interface Timing
Figure 31
Timing of the Microcontroller Interface
Parameter
Symbol
Limit Values
typ.
Unit
min.
1/8192
0.4*
t
DCLK
t
DCLK
/2
10
30
10
10
30
30
max.
Period of DCLK
DCLK high time
CS# setup time
CS# hold time
DIN setup time
DIN hold time
DOUT delay time
1)
DOUT delay time to high Z
t
DCLK
t
DCLKh
t
CS_s
t
CS_h
t
DIN_s
t
DIN_h
t
dDOUT
t
dDOUThz
ms
μs
ns
ns
ns
ns
ns
ns
0.6*
t
DCLK
50
50
50
50
1)
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing,
and a second component t
C_Load
= 0.4ns*C
Load
/pF, caused by external circuitry (C-load).
t
dDOUT_min
+ t
C_Load
50
DCLK
CS#
DIN
DOUT
CS_S
t
High Imp.
t
DIN_S
DIN_H
t
t
dDOUT
dDOUThz
t
t
DCLKh
DCLK
t
t
CS_h
50%
2466_231
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