參數(shù)資料
型號(hào): PEF24901H
英文描述: ?Quad ISDN Echocancellation Circuit Digital Front-End for 4B3T Line Code?
中文描述: ?四整體數(shù)位服務(wù)網(wǎng)路Echocancellation電路數(shù)字前端4B3T線路碼的終結(jié)?
文件頁數(shù): 58/73頁
文件大小: 1618K
代理商: PEF24901H
PEB 2466
PEF 2466
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual
49
2001-02-20
8.6
PCM-Interface Timing
8.6.1
Single Clocking Mode
Figure 29
PCM Interface Timing in Single Clocking Mode
Parameter
Symbol
Limit Values
typ.
Unit
min.
1/8192
0.4*
t
PCLK
max.
1/128
0.6*
t
PCLK
Period of PCLK
PCLK high time
Period FSC
FSC setup time
FSC hold time
DRA/B setup time
DRA/B hold time
DXA/B delay time
1)
DXA/B delay time to high Z
TCA#/TCB# delay time on
TCA#/TCB# delay time off
t
PCLK
t
PCLKh
t
FSC
t
FSC_s
t
FSC_h
t
DR_s
t
DR_h
t
dDX
t
dDXhz
t
dTCon
t
dTCoff
ms
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
t
PCLK
/2
125
50
50
50
50
10
40
10
10
25
25
25
25
1)
Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by
external components C
Load
and R
Pullup.
:
t
C_Load
= 0.4ns*C
Load
/pF
t
C*R
= R
Pullup
*C
Load
; R
Pullup
>1.5k
t
dDX_min
+ t
C_Load
50
t
dTCon_min
+ t
C_Load
t
dTCoff_min
+ t
C*R
t
PCLK
PCLK
FSC
DRA/B
DXA/B
FSC_S
t
PCLKh
t
High Imp.
t
DR_S
DR_H
t
t
dDX
dDXhz
t
t
FSC_H
FSC
t
TCA#/TCB#
dTCon
t
t
dTCoff
50%
2466_229
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