參數(shù)資料
型號(hào)： PDSP16350
廠(chǎng)商： Mitel Networks Corporation
英文描述： I/Q Splitter/NCO(分裂器/數(shù)字化控制的晶體振蕩器（對(duì)精確，數(shù)字化的正弦和余弦波形提供一個(gè)解決方案）)
中文描述： 的I / Q分配器/士官（分裂器/數(shù)字化控制的晶體振蕩器（對(duì)精確，數(shù)字化的正弦和余弦波形提供一個(gè)解決方案））
文件頁(yè)數(shù)： 6/15頁(yè)
文件大?。?/td> 314K
代理商： PDSP16350
PDSP16350
6
A practical example can be used to illustrate the calcula-
tion. With a clock frequency of 10.73864 MHz, and the need
to generate an output frequency of 20 kHz, then the above
equation tells us we need a DIN value of 31996359. This
corresponds to a binary value of:
DIN33:0 = 00 0000 0001 1110 1000 0011 1001 1100 0111
The resolution would be 0.0006 Hz. It should be noted that
the accuracy of the PDSP16350 cannot be any better than the
accuracy of the incoming clock, and these resolutions are
based on perfect incoming waveforms.
Fixed Frequency, Modulated Amplitude
The MODE pin should be high if modulation of the output
waveforms is required. In this mode each of the output
waveforms is multiplied by the 16 bit, two’s complement,
value, present on the most significant 16 bits of the DIN port.
The phase increment register is normally loaded with the 18
bit value on the least significant portion of the DIN bus. It is also
possible to load the full 34 bits of the phase increment register
when greater accuracy is required, this is explained below.
When using the full 34 bits it is possible to obtain the same
frequency resolution as in the fixed amplitude mode described
earlier. When using 18 bit accuracy directly from the DIN bus
the correct phase increment value can be calculated as
follows :
Desired O/P Frequency
DIN value =
x 2
18
Clock Frequency
The frequency resolution is correspondingly reduced and
given by :
Clock Frequency
Resolution =
Hz
2
18
USING THE PDSP16350
Frequency, phase, and amplitude modulation are all pos-
sible with the PDSP16350. The former two requirements are
satisfied by the ability to change the phase increment value on
every clock cycle. The latter needs the addition of two multipli-
ers, which allow both sine and cosine to be modified by an
incoming waveform.
Fixed Frequency, Constant Amplitude
To generate sine and cosine outputs at a fixed frequency,
the MODE pin should be tied low, see Fig. 3. The phase
increment value required to generate the desired frequency
should be clocked into the internal phase increment register.
This value is entered via the DIN port with CEN low. If CEN
subsequently goes inactive (high), the value need not be
maintained on the input pins.
The correct phase increment value can be calculated as
follows :
Desired O/P Frequency
DIN value =
x 2
34
Clock Frequency
This will give a decimal value which must be converted to
a 34 bit binary number. The frequency resolution of the
generated waveforms will be :
Clock Frequency
Resolution =
Hz
2
34
With a 20 MHz clock this results in a frequency resolution
of 0.001 Hz. This can be improved by reducing the clock
frequency, with the Nyquist restraint being the limiting factor.
The latter states that the frequency of the generated waveform
must be no more than 50% of the input clock. In practice 40%
is a better limit to use, as previously discussed.
Fig. 4 Amplitude Modulation (18bit frequency accuracy)
1
2
3
4
5
CLK
RESET
DATA IN
RESULT
30
31
32
33
34
35
A
B
A
B
Device Reset
Apply first data
First Result Available
C
D
C
D
JUMP
MODE
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