參數(shù)資料
型號(hào): PDSP16488A MA
廠商: Mitel Networks Corporation
英文描述: Single Chip 2D Convolver with Integral Line Delays(單片2D環(huán)繞的圖象處理設(shè)備(帶集成延遲線))
中文描述: 二維卷積器的單芯片線時(shí)滯的積分(單片二維環(huán)繞的圖象處理設(shè)備(帶集成延遲線))
文件頁數(shù): 1/30頁
文件大小: 237K
代理商: PDSP16488A MA
PDSP16488A MA
1
FEATURES
I
The PDSP16488A is a fully compatible replacement
for the PDSP16488
I
8 or 16 bit pixels with rates up to 40 MHz
I
Window sizes up to 8 x 8 with a single device
I
Eight internal line delays
I
Supports interlace and frame to frame operations
I
Coefficients supplied from an EPROM or remote host
I
Expandable in both X and Y for larger windows
I
Gain control and pixel output manipulation
I
132 pin QFP
8
16
8
16
8
16
1
1
1
1
1
2
1
2
2
4
4
-
1
2
2
4
4
-
4
-
6
-
-
-
4
-
6
-
-
-
4
-
8
-
-
-
9
-
-
-
-
-
Pixel
3x3
5x5
7x7
9x9
11x11 15x15 23x23
Size
10MHz
10MHz
20MHz
20MHz
40MHz
40MHz
Max Pixel
Rate
Window size
*
*
* Maximum rate is limited to 30 MHz by line store expansion delays
Table 2 Devices needed to implement typical window sizes
Table 1 Single Device Configurations
40MHz
20MHz
10MHz
20MHz
10MHz
8
8
8
16
16
4
8
8
4
8
4
4
8
4
4
4x1024
4x1024
8x512
4x512
4x512
Data
Size
Window Size
Width X Depth
Max Pixel
Rate
Line
Delays
The PDSP16488A is a fully integrated, application spe-
cific, image processing device. It performs a two dimensional
convolution between the pixels within a video window and a
set of stored coefficients. An internal multiplier accumulator
array can be multi-cycled at double or quadruple the pixel
clock rate. This then gives the window size options listed in
Table 1.
An internal 32k bit RAM can be configured to provide
either four or eight line delays. The length of each delay can
be programmed to the users requirement, up to a maximum of
1024 pixels per line. The line delays are arranged in two
groups,which may be internally connected in series or may be
configured to accept separate pixel inputs. This allows inter-
laced video or frame to frame operations to be supported.
The 8 bit coefficients are also stored internally and can
be downloaded from a host computer or from an EPROM. No
additional logic is required to support the EPROM and a single
device can support up to 16 convolvers.
The PDSP16488A contains an expansion adder and
delay network which allows several devices to be cascaded.
Convolvers with larger windows can then be fabricated as
shown in Table 2.
Intermediate 32 bit precision is provided to avoid any
danger of overflow, but the final result will not normally occupy
all bits. The PDSP16488A thus provides a multiplier in the
output path, which allows the user to align the result to the
most significant end of the 32 bit word.
Fig. 1 Typical , Stand Alone, Real Time System
DELAYED
SYNC
PIXEL
CLOCK
GENERATOR
SYNC
EXTRACT
ADDR DATA
CLK
SYNC
BYPASS
AUX
DATA
EPROM
OUTPUT
DATA
POWER ON
RESET
RES
A/D
CONVERTER
OPTIONAL
FIELD
STORE
COMPOSITE
DATA
IN
PDSP
16488A
CONVOLVER
Rev
A
B
C D
Date
MAR 1993 JUL 1996 JAN1997
NOTE
Polyimide is used as an inter-layer dielectric and as
glassivation.
Polymeric material is also used for die attach which according
to the requirement in paragraph 1.2.1.b. (2) precludes
catagorising this device as fully compliant. In every other
respect this device has been manufactured and screened in full
accordance with the requirements of Mil-Std 883 (latest revi-
sion).
CHANGE NOTIFICATION
The change notification requirements of MIL-PRF-38535 will
be implemented on this device type. Known customers will be
notified of any changes since the last buy when ordering further
parts if significant changes have been made.
PDSP16488A MA
Single Chip 2D Convolver with Integral Line Delays
Supersedes January 1997 version, DS3742 - 3.1
DS3742 - 4.0 January 2000
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PDSP16488AMAACBR 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Single Chip 2D Convolver with Integral Line Delays
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PDSP16488B0AC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Convolver
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