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參數(shù)資料
| 型號： | PDSP16330ABOAC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | GT 2C 2#0 PIN PLUG |
| 中文描述： | 畢達(dá)哥拉斯處理器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 173K |
| 代理商： | PDSP16330ABOAC |
PDSP16330/A/B
2
FUNCTIONAL DESCRIPTION
The PDSP16330 converts incoming Cartesian Data
into the equivalent Polar Values. The device accepts new 16
+ 16 bit complex data every cycle, and delivers a 16 bit + 12
bit Polar equivalent after 24 clock cycles.The input data can be
in 2s’ Complement or Sign Magnitude format selected via the
FORM input. The output is in a magnitude format for both the
Magnitude output and the Phase. Phase data is zero for data
with a zero Y input and positive X, and is 400 hex for zero X
data and positive Y, is 800 hex for zero Y data and negative X,
and is C00 hex for zero X and negative Y. The LSB weighting
(bit 0) is 2 x
π
/4096 radians. The 16 bit Magnitude result may
be scaled by shifting one, two, or three places in the more
significant direction, effectively multiplying the Magnitude
result by 2,4 or 8 respectively. Any of these shifts can under
certain conditions cause an invalid result to be output from the
device. Under these circumstances the OVR output will
become active. The PDSP16330 has independent clock
enables and three state output controls for all ports.
FORM
This input selects the format of the X and Y input data
.
A low level on FORM indlcates that the Input data is twos’
complement format (Note: input data 8000 hex is not valid in
2s’ complement mode). This input refers to the format of the
current Input data and may be changed on a per cycle basis
if desired. The level of FORM is latched at the same time as
the data to which it refers.
S1-0
These inputs select the scaling factor to be applied to
the Magnitude output. They are latched by the rising edge of
CLK and determine the scaling of the output in the cycle after
they are loaded into the device. The scale factor applied is
determined by the table. Should the scaling factor applied
cause an invalid Magnitude result to be output on the M Port,
then the OVR Flag will become active for the period that the
M Port output is invalid.
The output number range is from 0 to 2 when the
scaling factor is set at x1.
S0
0
1
0
1
Scaling Factor
x1
x2
x4
x8
S1
0
0
1
1
Fig.2 Block diagram
+
SHIFT
16
32
30
15
16
16
16
9
9
12
2
OEM
S0
S1
FORM
CEX
SIGN
15
30
SIGN X
SIGN Y
X > Y
OEP
P11:0
OVR
M15:0
X2
MAGNITUDE
MAGNITUDE
Y2
X2 + Y2
ROTATE
SIGN
Y/X
CEY
/4
π
ARCTAN
ROM
Y15:0
X15:0
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相關(guān)代理商/技術(shù)參數(shù) |
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| PDSP16330AC0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
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| PDSP16330AC0LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
| PDSP16330ACGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
| PDSP16330ACOAC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Pythagoras Processor |
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