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參數(shù)資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 4/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
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Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
4
5.0
PIN DESCRIPTION
Name
Pin Type
Pin Numbers
I/O
Description
AGND
Supply
32, 49, 52, 53
—
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
AVDD
Supply
30, 31, 43, 50, 51
—
Analog circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10
μ
F filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
CNA
CMOS
15
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
CPS
CMOS
24
I
Cable Power Status input. This terminal is normally connected to cable
power through a 390 k
resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
CTL0,
CTL1
CMOS 5V tol
3, 4
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P24 and the LLC. Bus holders are built into
these terminals.
C/LKON
CMOS 5V tol
18
I/O
Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10-k
resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
If the PDI1394P24 is used with an LLC that has a dedicated terminal for
monitoring LKON and also setting the contender status, then a 10-k
series resistor should be placed on the LKON line between the PHY and
LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI
(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.
Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.
DGND
Supply
2, 14, 25, 56, 64
—
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
D0–D7
CMOS 5V tol
5, 6, 8, 9, 10, 11,
12, 13
I/O
Data I/Os. These are bi-directional data signals between the
PDI1394P24 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 k
resistors.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
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