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參數(shù)資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 20/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
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Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
20
17.2
Forcing the RESET pin low resets the internal logic to the Reset
Start state and deactivates SYSCLK. Returning the RESET pin high
causes a Bus Reset condition on the active cable ports. For
power-up (and after Power Down is asserted) RESET must be
asserted low for a minimum of 2 ms from the time that the PHY
power reaches the minimum required supply voltage. This is
required to assure proper PLL operation before the PHY begins
using the clock. An internal pull-up resistor is connected to V
DD
, so
only an external delay capacitor is required. When using a passive
capacitor on the RESET terminal to generate a power-on reset
signal, the minimum reset time will be assured if the value of the
capacitor has a minimum value of 0.1
μ
F and also satisfies the
following equation:
RESET and Power Down
C
min
= 0.0077
×
T + 0.085
where C
min
is the minimum capacitance on the RESET terminal in
μ
F, and T is the V
DD
ramp time, 10%–90%, in ms.
An alternative to the passive reset is to actively drive RESET low for
the minimum reset time following power on. This input is a standard
logic Schmitt buffer and may also be driven by an open drain logic
output buffer.
The RESET pin also has a n-channel pull-down transistor activated
by the Power Down pin. For a reset during normal operation, a 10 us
low pulse on this pin will accomplish a full PHY reset. This pulse, as
well as the 2 ms power up reset pulse, could be microprocessor
controlled, in which case the external delay capacitor would not be
needed. For more details on using single capacitor isolation with this
pin, please refer to the Philips Isolation Application Note AN2452
The Power Down input powers down all device functions with the
exception of the CNA circuit to conserve power in portable or
battery-powered applications. It must be held high for at least 1.5 ms
to assure a successful reset after power down. This pin is equipped
with Bus Hold circuitry and supports an optional isolation barrier.
17.3
Using the PDI1394P24 with a non-P1394a
link layer
The PDI1394P24 implements the PHY-LLC interface specified in the
P1394a Supplement. This interface is based upon the interface
described in informative Annex J of IEEE Std 1394-1995, which is the
interface used in older PHY devices. The PHY-LLC interface specified
in P1394a is completely compatible with the older Annex J interface.
The P1394a Supplement includes enhancements to the Annex J
interface that must be comprehended when using the PDI1394P24
with a non-P1394a LLC device.
A new LLC service request was added which allows the LLC to
temporarily enable and disable asynchronous arbitration
accelerations. If the LLC does not implement this new service
request, the arbitration enhancements should not be enabled (see
the EAA bit in PHY register 5).
The capability to perform multispeed concatenation (the
concatenation of packets of differing speeds) was added in order
to improve bus efficiency (primarily during isochronous
transmission). If the LLC does not support multispeed
concatenation, multispeed concatenation should not be enabled in
the PHY (see the EMC bit in PHY register 5).
In order to accommodate the higher transmission speeds expected
in future revisions of the standard, P1394a extended the speed
code in bus requests from 2 bits to 3 bits, increasing the length of
the bus request from 7 bits to 8 bits. The new speed codes were
carefully selected so that new P1394a PHY and LLC devices would
be compatible, for speeds from S100 to S400, with legacy PHY and
LLC devices that use the 2-bit speed codes. The PDI1394P24
correctly interprets both 7-bit bus requests (with 2-bit speed code)
and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit
bus request is immediately followed by another request (e.g., a
register read or write request), the PDI1394P24 correctly interprets
both requests. Although the PDI1394P24 correctly interprets 8-bit
bus requests, a request with a speed code exceeding S400 results
in the PDI1394P24 transmitting a null packet (data-prefix followed
by data-end, with no data in the packet).
17.4
Using the PDI1394P24 with a lower-speed
link layer
Although the PDI1394P24 is an S400 capable PHY, it may be used
with lower speed LLCs. In such a case, the LLC has fewer data
terminals than the PHY, and some Dn terminals on the PDI1394P24
will be unused. Unused Dn terminals should be pulled to ground
through 10 k
resistors.
The PDI1394P24 transfers all received packet data to the LLC, even
if the speed of the packet exceeds the capability of the LLC to
accept it. Some lower speed LLC designs do not properly ignore
packet data in such cases. On the rare occasions that the first 16
bits of partial data accepted by such a LLC match a node’s bus and
node ID, spurious header CRC or tcode errors may result.
During bus initialization following a bus–reset, each PHY transmits a
self–ID packet that indicates, among other information, the speed
capability of the PHY. The bus manager (if one exists) builds a
speed–map from the collected self–ID packets. This speed–map
gives the highest possible speed that can be used on the
node–to–node communication path between every pair of nodes in
the network.
In the case of a node consisting of a higher–speed PHY and a
lower–speed LLC, the speed capability of the node (PHY and LLC in
combination) is that of the lower–speed LLC. A sophisticated bus
manager may be able to determine the LLC speed capability by
reading the configuration ROM Bus_Info_Block, or by sending
asynchronous request packets at different speeds to the node and
checking for an acknowledge; the speed–map may then be adjusted
accordingly. The speed–map should reflect that communication to
such a node must be done at the lower speed of the LLC, instead of
the higher speed of the PHY. However, speed–map entries for paths
that merely pass through the node’s PHY, but do not terminate at
that node, should not be restricted by the lower speed of the LLC.
To assist in building an accurate speed–map, the PDI1394P24 has
the capability of indicating a speed other than S400 in its transmitted
self–ID packet. This is controlled by the Link_Speed field in register
8 of the Vendor–Dependent page (page 7). Setting the Link_Speed
field affects only the speed indicated in the self–ID packet; it has no
effect on the speed signaled to peer PHYs during self–ID. The
PDI1394P24 identifies itself as S400 capable to its peers regardless
of the value in the Link_Speed field.
Generally, the Link_Speed field should not be changed from its
power–on default value of S400 unless it is determined that the
speed–map (if one exists) is incorrect for path entries terminating in
the local node. If the speed–map is incorrect, it can be assumed that
the bus manager has used only the self–ID packet information to
build the speed–map. In this case, the node may update the
Link_Speed field to reflect the lower speed capability of the LLC and
then initiate another bus–reset to cause the speed–map to be
rebuilt. Note that in this scenario any speed–map entries for
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