參數(shù)資料
型號(hào)： PCPIC
英文描述： PC(ISA)BUS I/O CARD
中文描述： 電腦（ISA）總線(xiàn)的I / O卡
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 468K
代理商： PCPIC
2192-09155-000-000
J230 PCPIC
Page 13
Bit
7
6
Name
Function
Comments
OUTPUT
NULL
state of output
Valid count data
1 = output pin high, 0 = output pin low
0 = counter data valid (count has been clocked from
count register into actual counter). 1 = not valid.
These two bits show how counter values are read and
written. They should be 11 = lower byte then upper
These three bits show the counter mode. For example,
101 = mode 5, 011 = mode 3
4/5
RWM1
read/write method
3
2
1
CM2
CM1
CM0
counter mode
counter mode
counter mode
0
BCD
If this bit is high the counter is a 4 digit BCD counter. If
low it is a 16-bit binary counter. It should be the latter.
For example, to set up counter 5 (wire 8 on the ribbon cable) to count
down from 515 (decimal) in mode 2 using binary counting we do the
following (assuming a board address of 180).
Write 0BH to 180H. This sets up the pointer to IC24's control
register. Counter 5 is IC24's counter 0.
Write 34H to 181H. This writes the bit pattern 00110100 into IC24's
control register. Check this against the register format above.
Write 08 to 180H. This sets up the pointer to IC24's counter 0
Write 3 to 181H. When 515 is turned into a 16-bit number the lower
byte is 3 and the upper is 2. We are writing both these bytes into the
counter in the order lower, upper.
Write 2 to 181H . Write the upper byte.
Note that the sub-section on how to write to the registers contains
more information about how the pointer scheme on the PCPIC
works.
Counter Modes
Each counter is made to operate in a particular mode by writing to
the control register. The modes are as follows:-
Mode 0: Interrupt on end of count.
The output changes from low to high when the end of count is
reached. The gate enables (when high) or disables the count.
Mode 1: Gate retriggerable one-shot.
A low-level pulse is output when the gate input is triggered (a
trigger is a low-to-high transition on the gate input).
Mode 2: Rate generator.
The output line goes low for one clock period when the count
reaches 0001. The counter operates as a frequency divider. Gate high
enables.
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