參數(shù)資料
型號： PCM9211PTR
廠商： TEXAS INSTRUMENTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, TOKEN RING TRANSCEIVER, PQFP48
封裝： GREEN, PLASTIC, LQFP-48
文件頁數(shù)： 76/121頁
文件大?。?/td> 1219K
代理商： PCM9211PTR
SDA
SCL
Start
Repeated Start
Stop
t
BUF
t
D-SU
t
D-HD
t
LOW
t
SCL-F
t
S-HD
t
HI
t
S-SU
t
SCL-R
t
S-HD
t
SDA-R
t
SDA-F
t
P-SU
t
GW
SBAS495 – JUNE 2010
www.ti.com
Timing Diagram
Figure 43 shows the detailed timing diagram for SCL and SDA.
STANDARD MODE
FAST MODE
SYMBOL
DESCRIPTION
MIN
MAX
MIN
MAX
UNITS
fSCL
SCL clock frequency
100
400
kHz
tBUF
Bus free time between STOP and START condition
4.7
1.3
s
tLOW
Low period of the SCL clock
4.7
1.3
s
tHI
High period of the SCL clock
4.0
0.6
s
tS-SU
Setup time for START/Repeated START condition
4.7
0.6
s
tS-HD
Hold time for START/Repeated START condition
4.0
0.6
s
tD-SU
Data setup time
250
100
ns
tD-HD
Data hold time
0
3450
0
900
ns
tSCL-R
Rise time of SCL signal
1000
20 + 0.1CB
300
ns
tSCL-F
Fall time of SCL signal
1000
20 + 0.1CB
300
ns
tSDA-R
Rise time of SDA signal
1000
20 + 0.1CB
300
ns
tSDA-F
Fall time of SDA signal
1000
20 + 0.1CB
300
ns
tP-SU
Setup time for STOP condition
4.0
0.6
s
tGW
Allowable glitch width
n/a
50
ns
CB
Capacitive load for SDA and SCL line
400
100
pF
Noise margin at High level for each connected device
VNH
0.2 × VDD
V
(including hysteresis)
Noise margin at Low level for each connected device
VNL
0.1 × VDD
0.1 × *VDD
V
(including hysteresis)
VHYS
Hysteresis of Schmitt-trigger input
n/a
0.05 × VDD
V
Figure 43. Control Interface Timing
58
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): PCM9211
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