- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367829 > PCM78P 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER PDF資料下載
參數(shù)資料
| 型號(hào)： | PCM78P |
| 英文描述： | 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | PCM78P |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
PCM78
11
state machine. This places stringent requirements on the
timing of the convert command, as improper timing can
cause metastable states within this state machine. Using the
circuitry shown in Figure 8, the user is assured of consistent
operation, and these invalid states within the state machine
are entirely avoided. (Note that this is not a consideration
when using an internal clock, as nothing is being clocked
when a convert command is presented to the PCM78).
The Clock Out function is a gated form of the external
clock, i.e. the 17 clock cycles used in the conversion are
present on this pin during conversion. This allows use of a
continuous external clock, with Clock Out being the clock
that the converter is actually using for conversion. Note that
this is simply a delayed (~24ns) version of the external
clock, and will have the same frequency and duty cycle.
The S
OUT2
Latch enables the user to latch data from the
previous conversion and read it out at a higher speed than
the convert clock. This feature allows the converter to
easily interface to digital filtering necessary for
oversampling. See Figure 9 for timing information in this
mode.
In this mode, the PCM78 generates its own internal convert
command when the S
OUT2
Clock goes high within
±
50ns of
S
OUT2
Latch going low; the external convert command may
not be used, and pin 19 must be grounded. The timing
diagram shows the recommended timing for using this
mode. After the S
OUT2
Latch control signal goes low, data
from the SAR is loaded into the S
OUT2
latch on the next
rising edge of the S
OUT2
Clock. This clock edge should
occur prior to the next rising edge of the conversion clock
(internal or external), since the SAR will reset itself prior to
the latching
In either case, the PCM78 requires 17 clock cycles to
complete a conversion. To calculate the clock frequency
necessary for a given conversion time, the following equa-
tion may be used:
The internal clock operates only during a conversion, and is
gated on by the falling edge of the convert command. See
Figure 6. The internal clock is available on pin 10, Clock
Out. The high and low time of this clock is set by R
1
C
1
and
R
2
C
2
respectively. The duty cycle of the clock should be
between 20% to 80%, and may be set to 50% for simplicity.
Clock High Time (in ns) = 1.32R
1
C
1
Clock Low Time (in ns) = 1.32R
2
C
2
R in k
; C in pF.
These equations are approximate (
±
5%); they should be
used for determining an initial part value which will then
need to be “tweaked” for accurate timing. If highly accurate
time bases are required, use of an external clock is recom-
mended.
The external clock is applied at pin 16, and the Int/Ext
Clock select (pin 17) should be left open (an internal pull-
up resistor assures that the logical state of an open pin is
“1”). Using the external clock requires careful placement in
time of the convert command. Figure 7 diagrams the recom-
mended timing with an external clock. A simple circuit
which assures the proper timing of the convert command is
shown in Figure 8.
Due to the design of the Clock/Logic chip in the PCM78, a
conversion is begun inside the PCM78 by an asynchronous
f
CLOCK
=
17
Conversion Time
T
4
Convert
Command
Clock Out
S
Data
Status
T
1
T
2
T
3
T
6
T
7
T
5
PCM78 TIMING SPECIFICATIONS
T
A
= +25
°
C, V
DD
= +5V, guaranteed by sample testing; these parameters are not 100% tested in production.
TIME (ns)
TYP
TIME
DESCRIPTION
MIN
MAX
T
1
T
2
T
3
T
4
T
5
T
6
T
7
CONVERT COMMAND pulse width
Delay from falling edge of CONVERT COMMAND to rising edge of CLOCK OUT
Delay from rising edge of CLOCK OUT to rising edge of STATUS
INTERNAL CLOCK pulse width
INTERNAL CLOCK period
Delay from rising edge of CLOCK OUT to bit data valid
Delay from rising edge of 17th clock pulse to falling edge of STATUS
25
60
8
50
140
17
10
50
70
10
125
290
20
15
(1)
85
30
450
500
50
30
NOTE: (1) When using the internal clock, the clock does not operate until the Convert Command is low. It is therefore possible to keep the convert command
high indefinitely, thereby keeping the PCM78 in a halt mode. The conversion cycle begins on the falling edge of convert command, and convert command must
remain low during the entire conversion cycle in order to make the PCM78 operate properly.
FIGURE 6. Conversion Timing when using Internal Clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCM78 | 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER |
| PCM95G | GEHAEUSE WASSERD DECKEL GRAU 230X140X95 |
| BMP | MOTAGEPLATTE FUER 223256 268 311 323 |
| PCM95T | GEHAEUSE WASSERD DECK TRANSP 230X140X95 |
| PCNET | PCnet - PCnet Family Network Driver Installation Guide. Part 2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM-79 | 功能描述:電線鑒定 Pre-Printed WM Card, Vinyl Cloth, .22" W RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| PCM-7T1 | 制造商:Panduit Corp 功能描述: |
| PCM-7T2 | 制造商:Panduit Corp 功能描述:Call vendor for pricing |
| PCM-8 | 功能描述:電線鑒定 1.5" VINYL CLOTH #8 RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| PCM-80 | 功能描述:電線鑒定 Pre-Printed WM Card, Vinyl Cloth, .22" W RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。