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參數(shù)資料
| 型號： | PCM78P |
| 英文描述： | 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 241K |
| 代理商： | PCM78P |
PCM78
10
FIGURE 4. Production Distortion + Noise Test System Block Diagram.
sample, and E
N
(i) is the residual noise energy present at
each sample. Similarly, THD alone can be expressed as
These expressions indicate that there is a correlation be-
tween THD+N and the square root of the sum of the squares
of the linearity errors at each digital word of interest. In
order to find this error at each code, a histogram test must
be performed on the PCM78, as illustrated in Figure 3. The
histogram for every converter is unique, as the linearity
errors from converter to converter will vary in their place-
ment along the transfer function. Typical histogram data is
shown in the Typical Curves.
However, this expression for THD+N does not mean that
the worst case linearity error of the A/D is directly corre-
lated to the THD+N because the digital output words from
theA/D vary according to the amplitude and frequency of
the sine wave input as well as the sampling frequency.
For the PCM78 the test sampling frequency was chosen to
be 200kHz, near the PCM78’s fastest rate of conversion.
The test frequencies used vary within the audio range, and
are stepped in amplitude from 0dB, to –20dB, to –60dB.
In manufacturing the PCM78, the test system shown in
Figure 4 is used to test for guaranteed THD+N.
ACCURACY VS CONVERSION
TIME AND INPUT SIGNAL LEVEL
The relationship of THD vs input signal level and THD vs
conversion time is shown is the typical curves. Slowing the
conversion time to more than 8
μ
s results in little added
benefit in terms of THD+N.
For applications which are not as concerned with dynamic
performance but require DC accuracy and linearity, it is
best to use the PCM78 at the longest conversion time
possible for the system requirements. Slowing the PCM78
to 8
μ
s-10
μ
s conversion time results in a substantial im-
provement in linearity. The typical curves show DNL and
INL plots for a typical device, at an 8
μ
s conversion time.
Due to the segmented architecture of the internal DAC used
in the successive approximation conversion technique, sig-
nificant differential linearity errors occur near bits 3 and 4.
Allowing more settling time for the DAC (by slowing the
conversion speed) will improve this differential linearity
error and give equivalent performance to more costly DC-
specified 12-bit to 14-bit A/D converters.
SYSTEM DESIGN
CONSIDERATIONS
DIGITAL CIRCUIT CONNECTIONS
The PCM78 comes complete with an internal clock circuit,
or it may be clocked by an external clock. Choosing which
mode to operate with depends upon the application for
which the PCM78 will be used. In an application where the
sample rate may not be fixed (transient recording, etc.),
using the internal clock set to give a very fast conversion
may be the best solution. In systems where the sample rate
is fixed, an external clock is probably the better choice since
it will allow the digital system design to be synchronous.
THD
=
1
N
E
L
i
()
2
i
=
1
E
rms
∑
X 100%
FIGURE 5. Timing Diagram for Figure 4.
Low-Pass
Filter
Distortion
Tester
S/H Control
Latch Enable
Status
B S C
Deglitcher Control
A
D
0
20
40
60
80
100
1201
100
A
Frequency (MHz)
10
LOW-PASS FILTER
CHARACTERISTICS
Shibasoku
AG16A
or
Equivalent
Shibasoku
AG16A
or
Equivalent
Toko Model
298BLR-002N
or PCM11 or
Equivalent
Convert
Command
MSB Adjust
Program-
mable
Gain Amp
DUT
PCM78P
Latch
74LS164
74LS273
16-Bit
DAC
Deglitcher
S/H
Amplifier
Audio
Oscillator
Timing
Control
Logic
Reference
Clock
A(S/H)
B
(CC)
S
(Status)
(Clock)
C
(Data Latch)
D
(Deglitcher
Control)
1 2 3 4
151617
50ns
<8μs
8.5μs
500ns
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