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參數(shù)資料
| 型號(hào)： | PCM78 |
| 英文描述： | 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 241K |
| 代理商： | PCM78 |
PCM78
15
MSB Adjustment
Differential Linearity errors at bipolar zero and THD are
guaranteed to meet data sheet specifications without any
external adjustment. However, a provision has been made
for an optional adjustment of the MSB linearity point which
makes it possible to eliminate DLE error at BPZ. This is
important when the signal level is very low, because zero
crossing noise (DLE at BPZ) becomes very significant when
compared to the small codes changes occurring in the LSB
portion of the converter.
The PCM78 is laser trimmed for best performance at the
factory without the MSB adjust circuitry installed; if better
performance can be obtained it would be by the addition of
the MSB adjust circuitry shown in Figure 16.
The best method of adjusting the MSB is by using a real time
FFT routine to monitor the levels of odd order harmonics
when a sine-wave is being digitized by the PCM78.
Adjusting the potentiometer in Figure 16 will allow the user
to reduce the magnitude of odd-order harmonics.
An alternate method is to reconstruct the data out of the
PCM78 through a DAC, and measure THD+N on a
conventional distortion analyzer. Adjust the potentiometer
for minimum THD+N.
2
MSB ADJ
3
1M
200k
–V
CC
220k
24
V
POT
FIGURE 16. MSB Adjust Circuit.
APPLICATIONS INFORMATION
A typical digitization circuit, used on the demonstration
board available for the PCM78, is shown in Figure 20. The
connections and part values shown in this circuit have been
optimized for the best THD+N performance at a 200kHz
sample rate.
The PCM78 may be interfaced to many popular digital
signal processors, such as the TMS320, DSP56001, and the
DSP32. Suggested interface circuits for these processors are
shown in Figures 17-19.
S
D
Q
Q
Clk
R
S
D
Q
Q
Clk
R
+5V
+5V
Status
Clk Out
OUT1
S
Data In
ICK
ILD
NOTE: Set for
16-Bit external
ILD, ICK MSB
bit first
PCM78P
DSP32C
S
D
Q
Q
Clk
R
S
D
Q
Q
Clk
R
+5V
+5V
+5V
+5V
Status
Clk Out
OUT1
S
RXD
RXC
FSR
NOTE: FSM =
Bit Mode
PCM78P
DSP56001
FIGURE 18. PCM78 Interface to Motorola DSP56001 DSP
Processor.
FIGURE 19. PCM78 Interface to AT&T DSP16 & DSP32C
Processors.
1
PCM78
V
IN
–
+
OPA627
FIGURE 15. Buffer Amplifier for PCM78 Input.
S
D
Q
Q
Clk
R
S
D
Q
Q
Clk
R
+5V
+5V
+5V
+5V
Status
Clk Out
OUT1
S
DR
Clk R
FSR
NOTE: FSM = 1
PCM78P
TMS320C25/C30
FIGURE 17. PCM78 Interface to TMS320C25/C30 DSP
Processors.
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