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參數(shù)資料
| 型號： | PCM78 |
| 英文描述： | 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 241K |
| 代理商： | PCM78 |
PCM78
12
PCM78 TIMING SPECIFICATIONS
T
A
= +25
°
C, V
DD
= +5V, guaranteed by sample testing; these parameters are not 100% tested in production.
TIME (ns)
TYP
TIME
DESCRIPTION
MIN
MAX
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
EXTERNAL CLOCK pulse width
EXTERNAL CLOCK period
Delay from falling edge of EXTERNAL CLOCK to rising edge of CONVERT COMMAND
CONVERT COMMAND pulse width
Delay from falling edge of CONVERT COMMAND to rising edge of EXTERNAL CLOCK
Delay from falling edge of CONVERT COMMAND to rising edge of CLOCK OUT
Delay from rising edge of CLOCK OUT to rising edge of STATUS
Delay from rising edge of CLOCK OUT to bit data valid
Delay from rising edge of 17th clock pulse to falling edge of STATUS
50
140
–30
10
20
40
6
15
8
125
290
0
50
50
75
10
17
10
(1)
(1)
420
200
430
460
30
20
30
NOTE: (1) The PCM78 does not contain dynamic digital circuitry, and can be clocked as slowly as the user wishes. In typical applications, the longest clock
period may be as long as 1
μ
s.
T
1
Ext
Clock
Convert
Command
Clock Out
S
Data
Status
T
2
T
3
T
5
T
4
T
6
T
7
T
8
T
9
FIGURE 7. Conversion Timing when using External Clock.
The data read out on S
OUT2
is from the conversion
previously performed, while the data that is present on
S
OUT1
is the real time readout of the successive approxima-
tion as it occurs.
SHORT CYCLE
The PCM78 has the ability to be short cycled to a resolution
less than 16 bits. This is accomplished by driving the Short
Cycle pin (pin 18) low when the conversion is to be
terminated, and holding it low until the next convert
command is given. The circuit in Figure 11 will accomplish
this function.
if the convert clock rises before the S
OUT2
Clock. This
condition is avoided as long as the frequency of S
OUT2
Clock
is at least 1.5 times that of the conversion clock.
The internal convert command is generated upon S
OUT2
Latch going low, and its falling edge occurs upon the first
falling edge of S
OUT2
Clock after S
OUT2
Latch goes low.
S
OUT2
Latch should remain low for at least 2 cycles of S
OUT2
Clock to insure proper latching. In many applications, the
S
OUT2
Latch can be the 2f
S
signal present in many digital
audio systems, typically known as WDCK. Figure 10
includes an example of this application.
+5V
Sample
(Convert)
D
Q
C
D
Q
C
D
QQ3
Convert
Command
Q
1
Q
2
PCM78
Clock
(Ext)
Clock
Clock
PCM78
Clock (Ext)
Sample
(Convert)
Q
1
Q
2
Q
3
Convert
Command
FIGURE 8. Convert Command Timing Circuit for Use with External Clock.
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