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參數(shù)資料
| 型號： | PCM58J |
| 英文描述： | Precision, 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 精密，18位單片音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 64K |
| 代理商： | PCM58J |
PCM58P
5
“STOPPED-CLOCK” OPERATION
The PCM58P is normally operated with a continuous clock
input signal. If the clock is to be stopped in between input
data words, the last 18-bits shifted in are not actually shifted
from the serial register to the latched parallel DAC register
until LE (latch enable) goes low. If the clock input (P16,
CLK) is stopped between data words, LE (P17) must remain
low until after the first clock cycle of the next data word
to insure proper DAC operation. In either case, the setup and
hold times for DATA and LE must still be observed as shown
in Figure 3.
INSTALLATION
Refer to Figure 4 for proper connection of the PCM58P in
the voltage-out mode using the internal feedback resistor.
The feedback resistor connections (P7 and P10) should be
connected to ACOM (P8) if not used. The PCM58P requires
only a +5V and –12V supply. It is very important that these
supplies be as “clean” as possible to reduce coupling of supply
noise to the output. Power supply decoupling capacitors
shown in Figure 4 should be used, regardless of how good
the supplies are to maximize power supply rejection. All
grounds should be connected to the analog ground plane as
close to the PCM58P as possible.
FILTER CAPACITOR REQUIREMENTS
As shown in Figure 4, other various decoupling capacitors
are required around the supply and reference points with no
special tolerances being required. Placement of all capacitors
should be as close to the appropriate pins of the PCM58P
as possible to reduce noise pickup from surrounding circuitry.
FIGURE 4. PCM58P Connection Diagram.
FIGURE 3. PCM58P Setup and Hold Timing Diagram.
Data
Input
>40ns
LSB
MSB
>15ns >15ns
Clock
Input
>40ns
>40ns
>5ns
>100ns
>15ns
Latch
Enable
>One Clock Cycle
>One Clock Cycle
Optional External Op-Amp
Burr-Brown
OPA602BP
NOTE: Connect P7 and P10 to P8
(ACOM) if internal feedback resis-
tor is not used
Optional
Bit
Adjust
Circuit
3.3μF
+
3.3μF
0.1μF
0.1μF
0.1μF
+
+5V
CAP
+V
CC
CAP
CAP
BPO
I
OUT
R
F1
ACOM
–V
CC
R
F2
DCOM
NC
+V
CC
NC
V
POT
Bit Adj (MSB)
Bit Adj (B2)
Bit Adj (B3)
Bit Adj (B4)
NC
NC
NC
–V
CC
DATA
NC
LE
CLK
CAP
0.1μF
3.3μF
–12V
330k
330k
330k
330k
100k
1k
1k
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