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參數(shù)資料
| 型號(hào)： | PCM58J |
| 英文描述： | Precision, 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 精密，18位單片音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | PCM58J |
PCM58P
4
In terms of signal measurement, THD+N is the ratio of
Distortion
+ Noise
/ Signal
expressed in dB. For
the PCM58P, THD+N is 100% tested at three different output
levels using the test setup shown in Figure 1. It is significant
to note that this test setup does not include any output
deglitching circuitry. This means the PCM58P even meets
its –60dB THD+N specification without use of external
deglitchers.
ABSOLUTE LINEARITY
Even though absolute integral and differential linearity specs
are not given for the PCM58P, the extremely low THD+N
performance is typically indicative of 15-bit to 16-bit integral
linearity in the DAC depending on the grade specified. The
relationship between THD+N and linearity, however, is not
such that an absolute linearity specification for every indi-
vidual output code can be guaranteed.
IDLE CHANNEL SNR
Another appropriate spec for a digital audio converter is idle
channel signal-to-noise ratio (idle channel SNR). This is the
ratio of the noise on the DAC output at bipolar zero in relation
to the full scale range of the DAC. The output of the DAC
is band-limited from 20Hz to 20kHz and an A-weighted filter
is applied to make this measurement. The idle channel SNR
for the PCM58P is typically greater than +126dB, making
it ideal for low-noise applications.
OFFSET, GAIN, AND TEMPERATURE DRIFT
Although the PCM58P is primarily meant for use in dynamic
applications, specifications are also given for more traditional
DC parameters such as gain error, bipolar zero offset error,
and temperature gain drift and offset drift.
TIMING CONSIDERATIONS
The PCM58P accepts TTL-compatible logic input levels.
Noise immunity is enhanced by the use of Schmitt trigger
input architectures on all input signal lines. The data format
of the PCM58P is binary two’s complement (BTC) with the
most significant bit (MSB) being first in the serial input bit
stream. Table I describes the exact input data to voltage output
coding relationship. Any number of bits can precede the 18
bits to be loaded as only the last 18 will be transferred to
the parallel DAC register after LE (P17; latch enable) has
gone low.
The individual DAC serial input data bit shifts transfer are
triggered on positive CLK edges. The serial to parallel data
transfer to the DAC occurs on the falling edge of LE (P17).
Refer to Figure 2 for graphical relationships of these signals.
MAXIMUM CLOCK RATE
The maximum clock rate of 16.9mHz for the PCM58P is
derived by multiplying the standard audio sample rate of
44.1kHz times sixteen (16X oversampling) times the standard
audio word bit length of 24 (44.1kHz x 16 x 24 = 16.9mHz).
Note that this clock rate accommodates a 24-bit word length,
even though only 18 bits are actually being used.
NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream.
(2) Data format is binary two’s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must
remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative.
DIGITAL INPUT
ANALOG OUTPUT
Binary Two’s
Complement (BTC)
Voltage (V)
V
OUT
Mode
Current (mA)
I
OUT
Mode
DAC Output
3FFFF Hex
20000 Hex
1FFFF Hex
00000 Hex
+FS
BPZ
+2.9999943
0.0000000
–0.0000057
–3.0000000
–0.9999981
0.0000000
+0.0000019
+1.0000000
BPZ – 1LSB
–FS
TABLE I. PCM60P Input/Output Relationships.
FIGURE 2. PCM58P Timing Diagram.
P16 (Clock)
1
MSB
P18 (Data)
P17 (Latch Enable)
2
3
4
10
11
12
13
14
15
16
17
18
LSB
1
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