參數(shù)資料
型號: PCM4104PFBR
英文描述: High-Performance, 24-Bit, 216kHz sampling, Four-channel Audio Digital-to-Analog Converter
中文描述: 高性能24位,216kHz的采樣,四通道音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 29/36頁
文件大?。?/td> 486K
代理商: PCM4104PFBR
$%
SBAS291C AUGUST 2003 REVISED DECEMBER 2004
www.ti.com
29
Register 6: System Control Register
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
RST
0
0
0
PDN34
PDN12
FS1
FS0
This register controls various system level functions of the PCM4104, including sampling mode, power down, and soft
reset.
FS[1:0]
Sampling Mode
FS1
0
0
1
1
FS0
0
1
0
1
Sampling Mode
Single Rate (default)
Dual Rate
Quad Rate
Not Used
PDN12
Power-Down for Channels 1 and 2
PDN12
0
1
Power Down for Channels 1 and 2
Disabled (default)
Enabled
PDN34
Power Down for Channels 3 and 4
PDN34
0
1
Power Down for Channels 3 and 4
Disabled (default)
Enabled
RST
Software Reset (value defaults to 0)
Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external reset
applied at the RST input (pin 9).
Register 7: Audio Serial Port Control Register
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
0
0
BCKE
LRCKP
0
FMT2
FMT1
FMT0
This register is used to control the data format and clock polarity for the PCM4104 audio serial port.
FMT[2:0]
Audio Data Format
FMT2
0
0
0
0
1
1
1
1
FMT1
0
0
1
1
0
0
1
1
DEM0
0
1
0
1
0
1
0
1
Data Format
24-bit left justified (default)
24-bit I
2
S
TDM with zero BCK delay
TDM with one BCK delay
24-bit right justified
20-bit right justified
18-bit right justified
16-bit right justified
LRCKP
LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0.
BCKE
BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.
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PCM4104PFBT High-Performance, 24-Bit, 216kHz sampling, Four-channel Audio Digital-to-Analog Converter
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