參數(shù)資料
型號(hào)： PCM3794RHBRG4
元件分類(lèi)： Codec
英文描述： 16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital Speaker Amplifier
中文描述： 16位，低功耗立體聲音頻編解碼器麥克風(fēng)偏置，耳機(jī)，揚(yáng)聲器放大器和數(shù)字
文件頁(yè)數(shù)： 28/63頁(yè)
文件大?。?/td> 915K
代理商： PCM3794RHBRG4
www.ti.com
R0002-02
M: Master Device S: Slave Device
St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
Transmitter
M
M
M
S
Data Type
St
Slave Address
W
ACK
M
Reg Address
M
Sr
M
Slave Address
S
ACK
M
R
S
ACK
M
Sp
M
NACK
S
Read Data
Timing Diagram
SDA
SCL
t
(BUF)
t
(D-SU)
t
(D-HD)
Start
t
(LOW)
t
(S-HD)
t
(SCL-F)
t
(SCL-R)
t
(HI)
t
(RS-SU)
t
(RS-HD)
t
(SDA-F)
t
(P-SU)
t
(SDA-R)
Stop
t
(SP)
T0050-03
PCM3793
PCM3794
SLES193A–AUGUST 2006–REVISED SEPTEMBER 2006
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 34. Read Operation
PARAMETERS
CONDITIONS
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIN
MAX
100
UNIT
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
ns
f
SCL
t
(BUF)
t
(LOW)
t
(HI)
t
(RS-SU)
t
(S-HD)
t
(D-SU)
t
(D-HD)
t
(SCL-R)
t
(SCL-R1)
SCL clock frequency
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for START condition
Hold time for START condition
Data setup time
Data hold time
Rise time of SCL signal
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitive load for SDA and SCL line
Pulse duration of suppressed spike
4.7
4.7
4
4.7
4
250
0
900
1000
1000
20 + 0.1 C
B
20 + 0.1 C
B
t
(SCL-F)
t
(SDA-R)
t
(SDA-F)
t
(P-SU)
C
B
t
(SP)
Standard
Standard
Standard
Standard
20 + 0.1 C
B
20 + 0.1 C
B
20 + 0.1 C
B
1000
1000
1000
ns
ns
ns
μ
s
pF
ns
4
400
25
Figure 35. I
2
C Interface Timing
28
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