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參數(shù)資料
| 型號： | PCM3501E |
| 元件分類： | Codec |
| 英文描述： | Low Voltage, Low Power, 16-Bit, Mono VOICE/MODEM CODEC |
| 中文描述： | 低電壓，低功耗，16位，單聲道語音/調(diào)制解調(diào)器編解碼器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | PCM3501E |
15
PCM3501
SERIAL
INTERFACE
MODE
M/S (PIN 6)
FS (PIN)
BCK (PIN 8)
0
1
Slave
Master
Input
Output
Input
Output
TABLE II. Master/Slave Mode Selection.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
BCKP
t
BCKH
t
BCKL
t
CKFS
t
FSW
t
FSP
t
DISU
t
DIHD
t
CKDO
t
R
t
F
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
Delay Time BCK Falling Edge to FS
FS Pulse Width HIGH
FS Period
DIN Set Up Time to BCK Rising Edge
DIN Hold Time to BCK Rising Edge
Delay Time BCK Falling Edge to DOUT
Rising Time of All Signals
Falling Time of All Signals
2400
1200
1200
– 40
16000
8000
8000
40
t
BCKP
+ 60
ns
ns
ns
ns
ns
t
BCKP
– 60
t
BCKP
1/f
S
60
60
0
ns
ns
ns
ns
ns
80
30
30
FIGURE 8. Serial Interface Timing for Master Mode.
MASTER/SLAVE OPERATION
The serial interface supports both Slave and Master Mode
operation. The mode is selected by the M/S input (pin 6).
Table II shows mode and pin settings corresponding to the
M/S input selection. Figure 9 shows connections for Slave
and Master mode operation.
FIGURE 9. Slave and Master Mode Connections.
Slave Mode Operation
In Slave Mode, the FS and BCK pins are inputs to the
PCM3501. Both FS and BCK should be derived from the
system clock signal (XTI or SCKIO) to ensure proper
synchronization. Slave Mode is best suited for applications
where the DSP or controller is capable of generating the FS,
BCK, and system clocks using an on-chip serial port and/or
timing generator.
Master Mode Operation
In Master Mode operation, both FS and BCK are clock
outputs generated by the PCM3501 from the system clock
input (XTI, SCKIO, or a crystal). In Master Mode, the timing
and phase relationships between system clock, FS, and BCK
are managed internally to provide optimal synchronization.
t
FSW
t
CKFS
t
BCKP
t
BCKH
t
DISU
t
DIHD
t
BCKL
t
CKDO
t
FSP
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FS, BCK signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
FS
(output)
BCK
(output)
DIN
(input)
DOUT
(output)
XTI
FS (input)
BCK (input)
DIN
DOUT
M/S
TSC
GND
GND
Controller
System
Clock
Slave Mode
PCM3501
XTI
FS (output)
BCK (output)
DIN
M/S
TSC
V
DD
GND
PCM3501
System
Clock
Controller
Master Mode
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