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參數(shù)資料
| 型號： | PCM3501E |
| 元件分類： | Codec |
| 英文描述： | Low Voltage, Low Power, 16-Bit, Mono VOICE/MODEM CODEC |
| 中文描述： | 低電壓，低功耗，16位，單聲道語音/調(diào)制解調(diào)器編解碼器 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | PCM3501E |
13
PCM3501
Reset and Power Down
The PCM3501 supports power-on reset, external reset, and
power-down operations. Power-on reset is performed by
internal circuitry automatically at power up, while the exter-
nal reset is initiated using the PDWN input (pin 20).
Power-on reset occurs when power and system clock are
initially applied to the PCM3501. The internal reset cir-
cuitry requires that the system clock be active at power up,
with at least three system clock cycles occurring prior to
V
DD
= 2.2V. When V
DD
exceeds 2.2V, the power-on reset
comparator enables the initialization sequence, which re-
quires 1024 system clock periods for completion. During
the initialization sequence, the DAC output is forced to
AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 3 and 5 for
power-on reset and post-reset delay timing.
External reset is performed by first setting PDWN = ‘0’ and
then setting PDWN = ‘1’. The LOW to HIGH transition on
PDWN causes the reset initialization sequence to start.
During the initialization sequence, the DAC output is forced
to AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 4 and 5 for
external reset and post-reset delay timing.
Power-down mode is enabled by setting PDWN = ‘0’.
During power-down mode, minimum current is drawn when
the system clock is removed, resulting in 60
μ
A (typical)
power supply current. The PDWN input includes an internal
pull-down resistor, which places the PCM3501 in power-
down mode at power-up if the PDWN pin is left uncon-
nected. Ideally, the PDWN input should be driven by active
logic in order to control reset and power-down operation. If
the PDWN pin is to be unused in the system application, it
should be connected to V
DD
to enable normal operation. By
setting PDWN = ‘1’ when exiting power-down mode, the
PCM3501 will initiate an external reset as described earlier
in this section.
1024 System Clock Periods
Reset
Reset Removal
2.4V
2.2V
2.0V
V
DD
Internal Reset
System Clock
FIGURE 3. Power-On Reset Timing.
1024 System Clock Periods
Reset
Reset Removal
System Clock
Internal Reset
PDWN
t
RST
PWDN = LOW Pulse Width
t
RST
= 40ns minimum
FIGURE 4. External Reset Timing.
FIGURE 5. DAC and ADC Output for Reset and Power Down.
Reset
Power Down
GND
V
COM
(0.5V
CC
)
Ready/Operation
Internal Reset
or Power Down
ADC DOUT
DAC V
OUT
High Impedance
(1)
t
ADCDLY1
(2304/f
S
)
t
DACDLY1
(2048/f
S
)
Reset Removal or Power Down OFF
NOTE: (1) The HPF transient response (exponentially attenuated signal from
±
0.2% DC of FSR with 200ms time constant) appears initially.
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