參數(shù)資料
型號(hào)： PCM3001
元件分類： Codec
英文描述： Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM
中文描述： 立體聲音頻編解碼器18位，串行接口商標(biāo)
文件頁(yè)數(shù)： 20/21頁(yè)
文件大?。?/td> 212K
代理商： PCM3001
20
PCM3000/3001
VCOM INPUTS
A 4.7
μ
F to 10
μ
F tantalum capacitor is recommended be-
tween VCOM and AGND to ensure low source impedance
of the DAC output common. This capacitor should be
located as close as possible to the VCOM pin to reduce
dynamic errors on the DAC common.
SYSTEM CLOCK
The quality of the system clock can influence dynamic
performance of both the ADC and DAC in the PCM3000/
3001. The duty cycle, jitter, and threshold voltage at the
system clock input pin must be carefully managed. When
power is supplied to the part, the system clock, bit clock
(BCKIN) and a word clock (LCRIN) should also be supplied
simultaneously. Failure to supply the audio clocks will result
in a power dissipation increase of up to three times normal
dissipation and may degrade long term reliability if the
maximum power dissipation limit is exceeded.
THEORY OF OPERATION
ADC SECTION
The PCM3000/3001 ADC consists of a bandgap reference,
a stereo single-to-differential converter, a fully differential
5th-order delta-sigma modulator, a decimation filter (includ-
ing digital high pass), and a serial interface circuit. The
Block Diagram in this data sheet illustrates the architecture
of the ADC section, Figure 1 shows the single-to-differential
converter, and Figure 14 illustrates the architecture of the
5th-order delta-sigma modulator and transfer functions.
An internal high precision reference with two external ca-
pacitors provides all reference voltages which are required
by the ADC, which defines the full scale range for the
converter. The internal single-to-differential voltage con-
verter saves the space and extra parts needed for external
circuitry required by many delta-sigma converters. The
internal full differential signal processing architecture pro-
vides a wide dynamic range and excellent power supply
rejection performance.
The input signal is sampled at 64X oversampling rate,
eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a one-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of
the audio band in the frequency domain. The high order of
the modulator enables it to randomize the modulator out-
puts, reducing idle tone levels.
The 64f
S
one-bit data stream from the modulator is con-
verted to 1f
S
18-bit data words by the decimation filter,
which also acts as a low pass filter to remove the shaped
quantization noise. The DC components are removed by a
high pass filter function contained within the decimation
filter.
THEORY OF OPERATION
DAC SECTION
The delta-sigma DAC section of PCM3000/3001 is based on
a 5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format. A block diagram of the 5-level delta-
sigma modulator is shown in Figure 15. This 5-level delta-
sigma modulator has the advantage of improved stability
and reduced clock jitter sensitivity over the typical one-bit
(2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 64f
S
for a
256f
S
system clock. The theoretical quantization noise per-
formance of the 5-level delta-sigma modulator is shown in
Figure 16.
相關(guān)PDF資料
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PCM3001E Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM
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