參數(shù)資料
型號： PCM3001
元件分類： Codec
英文描述： Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM
中文描述： 立體聲音頻編解碼器18位，串行接口商標(biāo)
文件頁數(shù)： 17/21頁
文件大?。?/td> 212K
代理商： PCM3001
17
PCM3000/3001
REGISTER
NAME
BIT
NAME
DESCRIPTION
Register 0
A (1:0)
res
LDL
AL (7:0)
Register Address “00”
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Lch
Attenuation Data for Lch
Register 1
A (1:0)
res
LDR
AR (7:0)
Register Address “01”
Reserved, should be set to “0”
DAC Attenuation Data Load Control for Rch
DAC Attenuation for Rch
Register 2
A (1:0)
res
PDWN
BYPS
ATC
IZD
OUT
DEM (1:0)
MUT
Register Address “10”
Reserved, should be set to “0”
ADC Power Down Control
ADC High-Pass Filter Operation Control
DAC Attenuation Data Mode Control
DAC Infinite Zero Detection Circuit Control
DAC Output Enable Control
DAC De-emphasis Control
Lch and Rch Soft Mute Control
Register 3
A (1:0)
res
LOP
FMT (2:0)
LRP
Register Address “11”
Reserved, should be set to “0”
ADC/DAC Analog Loop-back Control
ADC/DAC Audio Data Format Selection
ADC/DAC Polarity of LR-clock Selection
TABLE III. Functions of the Registers.
PROGRAM REGISTER (PCM3000)
The software mode allows the user to control special functions.
PCM3000’s special functions are controlled using four pro-
gram registers which are 16 bits long. There are four distinct
registers, with bits 9 and 10 determining which register is in
use. Table III describes the functions of the four registers.
PROGRAM REGISTER 0
A (1:0):
Bit 10, 9
Register Address
These bits define the address for REGISTER 0:
A1
A0
0
0
Register 0
res:
Bit 11 : 15
These bits are reserved and should be set to “0”.
Bit 8
DAC Attenuation Data Load Control for
Left Channel
Reserved
LDL:
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
new attenuation data will be stored into a register,
and the output level will remain at the previous
attenuation level. The LDR bit in REGISTER 1
has the equivalent function as LDL. When either
LDL or LDR is set to “1”, the output level of the
left and right channels are simultaneously con-
trolled.
AL (7:0): Bit 7 :0
DAC Attenuation Data for Left Channel
AL7 and AL0 are MSB and LSB, respectively.
The attenuation level (ATT) is given by:
ATT = 20
x
log
10
(ATT data/256) (dB)
AL (7:0)
ATTENUATION LEVEL
00h
01h
:
FEh
FFh
–
∞
dB (Mute)
–48.16dB
:
–0.07dB
0dB (default)
PROGRAM REGISTER 1
A (1:0):
Register Address
These bits define the address for REGISTER 1:
A1
A0
0
1
Register 1
res:
Bit 15 : 11
These bits are reserved and should be set to “0”
Bit 8
DAC Attenuation Data Load Control for
Right Channel
Reserved
LDR:
This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AR (7:0) attenuation data
when this bit is set to “1”. When set to “0”, the
new attenuation data will be stored into a register,
and the output level will remain at the previous
attenuation level. The LDL bit in REGISTER 0
has the equivalent function as LDR. When either
LDL or LDR is set to “1”, the output level of the
left and right channels are simultaneously con-
trolled.
AR (7:0): Bit 7 : 0
DAC Attenuation Data for Right
Channel
AR7 and AR0 are MSB and LSB respectively.
See REGISTER 0 for the attenuation formula.
PROGRAM REGISTER 2
A (1:0):
Bit 10, 9
Register Address
These bits define the address for REGISTER 2:
A1
A0
1
0
Register 2
res:
Bit 15:11, 6 Reserved
These bits are reserved and should be set to “0”.
Bit 8
ADC Power-Down Control
This bit places the ADC section in a power-down
mode, forcing the output data to all zeroes. This
has no effect on the DAC section.
PDWN:
PDWN
0
1
Power Down Mode Disabled (default)
Power Down Mode Enabled
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