參數(shù)資料
型號(hào): PCM1851APJTRG4
英文描述: 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 ⅴ 2-CHANNEL MUX AND PGAE
中文描述: 24位,96千赫立體聲A / D轉(zhuǎn)換器6ⅴ2通道MUX和PGAE
文件頁(yè)數(shù): 24/32頁(yè)
文件大小: 409K
代理商: PCM1851APJTRG4
www.ti.com
CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850A)
Figure 29
shows a detailed timing diagram for the serial control interface of the PCM1850A. These timing
parameters are critical for proper control port operation.
t
(MCH)
1.4 V
MS
t
(MSS)
LSB
1.4 V
1.4 V
t
(MCL)
t
(MHH)
t
(MSH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
T0013-06
I
2
C SERIAL CONTROL PORT FOR MODE CONTROL (PCM1851A)
The user-programmable built-in function of the PCM1851A can be controlled through the I
2
C-format serial control
port, SDA (pin 32) and SCL (pin 31). The PCM1851A supports the I
2
C serial bus and the data transmission
protocol for standard mode as a slave device. This protocol is explained in I
2
C specification 2.0.
Slave Address
MSB
Packet Protocol
PCM1850A
PCM1851A
SLES173–MARCH 2006
SYMBOL
t
(MCY)
t
(MCL)
t
(MCH)
t
(MHH)
t
(MSS)
t
(MSH)
t
(MDH)
t
(MDS)
PARAMETER
MIN
100
40
40
80
15
15
15
15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MC pulse cycle time
MC LOW-level time
MC HIGH-level time
MS HIGH-level time
MS falling edge to MC rising edge
MS hold time
(1)
MD hold time
MD setup time
(1)
MC rising edge for LSB to MS rising edge
Figure 29. PCM1850A Control Interface Timing
LSB
1
0
0
1
0
1
ADR
R/nW
The PCM1851A has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory
preset to 100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
pin (pin 30). A maximum of two PCM1851As can be connected on the same bus at one time. Each PCM1851A
responds when it receives its own slave address.
A master device must control packet protocol, which consists of start condition, slave address with read/write bit,
data if write or acknowledgement if read, and stop condition. The PCM1851A supports only slave receivers, so
the R/W bit must be set to 0.
24
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