參數資料
型號: PCM1851APJTRG4
英文描述: 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 ⅴ 2-CHANNEL MUX AND PGAE
中文描述: 24位,96千赫立體聲A / D轉換器6ⅴ2通道MUX和PGAE
文件頁數: 16/32頁
文件大?。?/td> 409K
代理商: PCM1851APJTRG4
www.ti.com
ANALOG FRONT END
The PCM1850A/1851A has a built-in analog front-end circuit, which is shown in the block diagram of
Figure 22
.
Selection of the multiplexer input and PGA gain is controlled by mode control via the serial port as shown in
Table 2
and
Table 3
. The change of the input selection and the gain selection is performed immediately after the
serial control packet for the change is sent. A popping noise or other unexpected transient response could be
generated in the audio signal during channel and gain change. Because the PCM1850A/1851A has no
zero-cross detection and no other buffering capability for channel and gain change, appropriate data handling in
the digital domain is recommended to control transients.
PGA
(11 dB to –11 dB)
with MUX
G = –1
V
REF
S
(= 0.5 V
CC
)
LIN+
R
V
IN
L1
R
V
IN
L6
R
V
IN
L2
V
REF
1
(= 0.5 V
CC
)
R
R
MOUTL
LIN–
B013101
PCM1850A
PCM1851A
SLES173–MARCH 2006
The PCM1850A/1851A analog front end permits only ac input via an input capacitor; dc input is prohibited. A
signal source resistance of less than 1 k
is recommended for the V
IN
xx pins.
All unselected channel inputs are terminated V
REF
S (= 0.5 V
CC
) using a resistor, typically 57 k
.
The PCM1850A/1851A employs MOUTL/R pins (pins 12 and 11) to monitor the multiplexer output. The load on
these pins must be ac-coupled and not less than 10 k
. The full-scale output level is typically 0.6 V
CC
.
Figure 22. Analog Front-End Block Diagram (L-Channel)
Table 2. Multiplexer Input Selection
CH2
0
0
0
0
1
1
1
1
CH1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
CHANNEL
Mute
Channel 1 (default)
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Mute
16
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