參數(shù)資料
型號: PCM1851APJTG4
英文描述: 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 ⅴ 2-CHANNEL MUX AND PGAE
中文描述: 24位,96千赫立體聲A / D轉(zhuǎn)換器6ⅴ2通道MUX和PGAE
文件頁數(shù): 25/32頁
文件大?。?/td> 409K
代理商: PCM1851APJTG4
www.ti.com
9
SDA
SCL
St
17
8
18
9
18
9
9
Sp
Slave Address
ACK
DATA
ACK
DATA
ACK
ACK
R/W
R/W:
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
Read Operation if 1; Otherwise, Write Operation
Stop
Condition
Start
Condition
Transmitter
M
M
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
ACK
Sp
M: Master Device
St: Start Condition
S: Slave Device
Sp: Stop Condition
T0049-05
Write Operation
R0002-03
M: Master Device S: Slave Device
St: Start Condition ACK: Acknowledge W: Write Sp: Stop Condition
Transmitter
M
M
M
S
Data Type
St
Slave Address
W
ACK
M
Reg Address
M
Write Data 1
S
ACK
S
ACK
M
Sp
M
Write Data 2
S
ACK
S
ACK
PCM1850A
PCM1851A
SLES173–MARCH 2006
Figure 30. Basic I
2
C Framework
The PCM1851A has only the write mode. A master can write to any PCM1851A registers using single or multiple
accesses. The master sends a PCM1851A slave address with a write bit, a register address, and the data. If
multiple access is required, the address is that of the starting register, followed by the data to be transferred.
When the data are received properly, the index register is incremented by 1 automatically. When the index
register reaches 33h, the next value is 31h. When undefined registers are accessed, the PCM1851A does not
send an acknowledgement.
Figure 31
is a diagram of the write operation. The register address and the write data
are 8 bits and MSB-first format.
Figure 31. Framework for Write Operation
25
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