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| 型號： | PCM1851APJTG4 |
| 英文描述： | 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 ⅴ 2-CHANNEL MUX AND PGAE |
| 中文描述： | 24位，96千赫立體聲A / D轉換器6ⅴ2通道MUX和PGAE |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 409K |
| 代理商： | PCM1851APJTG4 |
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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
In slave mode, the PCM1850A/1851A operates under LRCK, synchronized with system clock SCKI. The
PCM1850A/1851A does not need a specific phase relationship between LRCK and SCKI, but does require the
synchronization of LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than
±
6 BCKs for 64 BCKs/frame (
±
5 BCKs for 48
BCKs/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
S
and digital output is forced into the BPZ code until resynchronization between LRCK and SCKI is completed.
In the case of changes less than
±
5 BCKs for 64 BCKs/frame (
±
4 BCKs for 48 BCKs/frame), resynchronization
with simultaneous discontinuity in the digital output does not occur.
1/f
S
32/f
S
NORMAL DATA
ZERO DATA
UNDEFINED
DATA
NORMAL DATA
SYNCHRONOUS
ASYNCHRONOUS
SYNCHRONOUS
Resynchronization
Synchronization Lost
DOUT
State of Synchronization
T0020-05
Power-Down Control
Overflow Flag Output
HPF Bypass Control
PCM1850A
PCM1851A
SLES173–MARCH 2006
Figure 26
illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1850A/1851A might generate some noise in the audio signal. Also, the transition of
normal to undefined data and undefined or zero data to normal creates a discontinuity of data in the digital
output, which could generate some noise in the audio signal.
It is recommended to set RST (pin 10) to LOW to get stable analog performance when the sampling rate,
interface mode, or data format is changed.
Figure 26. ADC Digital Output for Loss of Synchronization and Resynchronization
RST (pin 10) controls the entire ADC operation. During reset mode, the supply current of the analog section is
shut off and the digital section is initialized. DOUT (pin 3) is also disabled. Halting SCKI, BCK, and LRCK is
recommended to minimize power dissipation.
RST
LOW
HIGH
POWER-DOWN MODE
Reset and power-down modes
Normal operation mode
The PCM1850A/1851A has an output flag (pin 4) that indicates when overflow occurs in the L-channel or
R-channel, and this flag remains HIGH at least during the 8192/f
S
time for a momentary overflow occurrence.
The built-in HPF function for dc component rejection can be bypassed via the serial port. In bypass mode, the dc
component of the analog input signal, the internal dc offset, etc., are converted and included in the digital output
data.
BYP
0
1
HPF (HIGH-PASS FILTER) MODE
Normal (no dc component on DOUT) mode (default)
Bypass (dc component on DOUT) mode
22
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| PCM1851APJTR | 功能描述:音頻模/數(shù)轉換器 IC 24-Bit Audio ADC RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
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| PCM1851PJTG4 | 功能描述:音頻模/數(shù)轉換器 IC 24-Bit Stereo ADC w/6x2 ch MUX & PGA RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| PCM1851PJTR | 功能描述:音頻模/數(shù)轉換器 IC 24-Bit Stereo ADC w/6x2 ch MUX & PGA RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
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