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| 型號： | PCM1808PW |
| 英文描述： | SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER |
| 中文描述： | 單端模擬輸入24位，96千赫立體聲A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 214K |
| 代理商： | PCM1808PW |
www.ti.com
CLOCK-HALT POWER-DOWN AND RESET FUNCTION
The PCM1808 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both master
and slave modes. The function is available anytime after power on. Reset and power down are performed
automatically 4
μ
s (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808 stays in
the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the
reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024
SCKI + 8960/f
S
has elapsed. Because the fade-in operation is performed, it takes additional time of 48/f
in
or
48/f
until the level corresponding to the analog input signal is obtained.
Figure 20
illustrates the clock-halt reset
timing.
Clock-Halt Reset
SCKI
T0081-01
48/f
in
or 48/f
S
Fade-In Start
Fade-In Complete
Internal
Reset
Operation
Operation
DOUT
Normal Data
Normal Data
DOUT
(Contents)
Normal Data
SCKI Halt
SCKI Resume
Fixed to Low or High
t
(CKR)
Reset: t
(RST)
Reset Release: t
(REL)
BPZ
Zero Data
PCM1808
SLES177A–APRIL 2006–REVISED AUGUST 2006
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI
within 4480/f
after SCKI is resumed. If it takes more than 4480/f
for BCK and LRCK to synchronize with SCKI,
SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the
typical circuit connection diagram,
Figure 26
.
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor
the audio interface clocks BCK and LRCK (sampling rate f
S
) are changed on the fly.
SYMBOL
t
(CKR)
t
(RST)
t
(REL)
PARAMETER
MIN
4
MAX
UNIT
μ
s
μ
s
μ
s
Delay time from SCKI halt to internal reset
Delay time from SCKI resume to reset release
Delay time from reset release to DOUT output
1024 SCKI
8960/f
S
Figure 20. Clock-Halt Power-Down and Reset Timing
13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1808PW | 制造商:Texas Instruments 功能描述:IC ADC 24BIT STER 96KHZ 14-TSSOP 制造商:Texas Instruments 功能描述:IC, ADC 24BIT STER 96KHZ 14-TSSOP 制造商:Texas Instruments 功能描述:IC, ADC 24BIT STER 96KHZ 14-TSSOP; Resolution (Bits):24bit; Sampling Rate:96kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Supply Current:10.2mA; Digital IC Case Style:TSSOP; No. of Pins:14; Input;RoHS Compliant: Yes |
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| PCM1808PWR | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC Sgl-ended Ana Input 24B 96kHz Stereo ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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| PCM1808QPWRQ1 | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AC 99dB SNR Stereo ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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