參數(shù)資料
型號(hào)： PCM1807PWR
英文描述： Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D Converter
中文描述： 單端模擬輸入24位，96千赫立體聲A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 25/29頁(yè)
文件大小： 426K
代理商： PCM1807PWR
www.ti.com
APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION DIAGRAM
Figure 31
is typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog
inputs, V
IN
L and V
IN
R. If the performance of these filters is not adequate for an application, appropriate external
antialiasing filters are needed. A passive RC filter (100
and 0.01
μ
F to 1 k
and 1000 pF) generally is used.
S0113-01
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+
5 V
V
IN
R
V
IN
L
MS
MC
MD
DOUT
BCK
V
REF
AGND
V
CC
V
DD
DGND
SCKI
LRCK
+
C
1(1)
+
C
2(1)
C
4(2)
3.3 V
C
5(3)
PCM1807
+
C
3(2)
+
4
μ
s (min)
Mask
X1
(4)
PLL170x
DSP
or
Audio
Processor
L-ch IN
R-ch IN
MCU
(5)
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
PINS
The digital and analog power supply lines to the PCM1807 should be bypassed to the corresponding ground pins
with both 0.1-
μ
F ceramic and 10-
μ
F electrolytic capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC.
AGND, DGND PINS
V
IN
L, V
IN
R PINS
V
IN
L and V
IN
R are single-ended inputs. The antialias low-pass filters are integrated on these inputs to remove the
noise outside the audio band. If the performance of these filters is not adequate for an application, appropriate
external antialiasing filters are required. A passive RC filter (100
and 0.01
μ
F to 1 k
and 1000 pF) is
generally used.
PCM1807
SLES147–SEPTEMBER 2005
(1)
C1, C2: A 1-
μ
F electrolytic capacitor gives 2.7 Hz (
τ
= 1
μ
F
×
60 k
) cutoff frequency for the input HPF in normal
operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period.
C3, C4: Bypass capacitors, 0.1-
μ
F ceramic and 10-
μ
F electrolytic, depending on layout and power supply
C5: 0.1-
μ
F ceramic and 10-
μ
F electrolytic capacitors are recommended.
X1: X1 masks the system clock input when using the clock-halt reset function with external control.
Optional external antialiasing filter could be required, depending on the application.
Figure 31. Typical Circuit Connection Diagram
(2)
(3)
(4)
(5)
To maximize the dynamic performance of the PCM1807, the analog and digital grounds are not internally
connected. These grounds should have low impedance to avoid digital noise feedback into the analog ground.
They should be connected directly to each other under the PCM1807 package to reduce potential noise
problems.
25
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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PCM1808PWR 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC Sgl-ended Ana Input 24B 96kHz Stereo ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
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