參數(shù)資料
型號(hào)： PCM1804DBR
英文描述： FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER
中文描述： 全差分模擬輸入24位，192千赫立體聲A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 19/31頁(yè)
文件大?。?/td> 470K
代理商： PCM1804DBR
PCM1804
SLES022A
–
DECEMBER 2001
19
www.ti.com
PRINCIPLES OF OPERATION
Table 2. Oversampling Ratio in Slave Mode
OSR2
Low
Low
Low
Low
High
High
High
High
OSR1
Low
Low
High
High
Low
Low
High
High
OSR0
Low
High
Low
High
Low
High
Low
High
OVERSAMPLING RATIO
Single rate (
×
128 fS)
Dual rate (
×
64 fS)
Quad rate (
×
32 fS)
Reserved
Reserved
Reserved
Reserved
Reserved
SYSTEM CLOCK RATE
Automatically detected
Automatically detected
Automatically detected
–
–
–
–
–
Table 3. Sampling Frequency and System Clock Frequency
OVERSAMPLING RATIO
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (MHz)
192 fS
256 fS
—
8.192
—
11.2896
—
12.288
—
22.5792
—
24.576
33.8688
36.864
—
16.9344 for 384 fS, 11.2896 for 256 fS
128 fS
—
—
—
—
—
22.5792
24.576
384 fS
12.288
16.9344
18.432
33.8688
36.864
—
—
512 fS
16.384
22.5792
24.576
—
—
—
—
768 fS
24.576
33.8688
36.864
—
—
—
—
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
176.4 kHz
192 kHz
44.1 kHz
Single rate (see Note 10)
Dual rate (see Note 11)
Quad rate (see Note 12)
DSD mode (see Note 11)
Only master mode
NOTES: 10. Modulator is running at 128 fS
11. Modulator is running at 64 fS
12. Modulator is running at 32 fS
1024 System Clock + 1/fS(max)
Reset
Reset Removal
4.4 V / 2.2 V
4 V / 2 V
3.6 V / 1.8 V
VCC / VDD
Internal Reset
System Clock
Figure 33. Internal Power-On Reset Timing
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