參數(shù)資料
型號: PCM1804DB
英文描述: FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER
中文描述: 全差分模擬輸入24位,192千赫立體聲A / D轉(zhuǎn)換器
文件頁數(shù): 22/31頁
文件大小: 470K
代理商: PCM1804DB
PCM1804
SLES022A
DECEMBER 2001
22
www.ti.com
PRINCIPLES OF OPERATION
interface timing for PCM (continued)
t(LRCP)
tw(BCKH)
tw(BCKL)
t(CKLR)
t(BCKP)
t(CKDO)
t(LRDO)
0.5 VDD
0.5 VDD
0.5 VDD
LRCK
BCK
DATA
PARAMETERS
MIN
TYP
MAX
UNIT
BCK period, t(BCKP)
BCK pulse width high, tw(BCKH)
BCK pulse width low, tw(BCKL)
Delay time BCK falling edge to LRCK valid, t(CKLR)
LRCK period, t(LRCP)
Delay time BCK falling edge to DATA valid, t(CKDO)
Delay time LRCK edge to DATA valid, t(LRDO)
Rising time of all signals, tr
Falling time of all signals, tf
1/(64 fS)
32
ns
32
ns
5
15
ns
1/fS
5
15
ns
5
15
ns
10
ns
10
ns
NOTES: A. Rising and falling time is measured from 10% to 90% of IN/OUT signals swing.
B. Load capacitance of all signals are 10 pF.
C. t(BCKP) is fixed at 1/(64 fS) in case of master mode.
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
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