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參數(shù)資料
| 型號： | PCM1801U |
| 英文描述： | 16-Bit, Stereo, Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，立體聲，音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 101K |
| 代理商： | PCM1801U |
12
PCM1801
SYNCHRONIZATION WITH
DIGITAL AUDIO SYSTEM
PCM1801 operates with LRCK synchronized to the system
clock (SCKI). PCM1801 does not require a specific phase
relationship between LRCK and SCKI, but does require the
synchronization of LRCK and SCKI. If the relationship
between LRCK and SCKI changes more than 6 bit clocks
(BCK) during one sample period due to LRCK or SCKI
jitter, internal operation of the ADC halts within 1/f
S
and the
digital output is forced to BPZ until resynchronization be-
tween LRCK and SCKI is completed. In case of changes less
than 5 bit clocks (BCK), resynchronization does not occur
and above digital output control and discontinuity does not
occur.
ADC DATA OUTPUT AT RESET
Figures 6 and 7 illustrate the ADC digital output for the reset
operation and loss of synchronization state. During undefined
data, it may generate some noise in the audio signal. Also, the
transition of normal to undefined data and undefined or zero
data to normal makes a discontinuity of data on the digital
output, and may generate some noise in the audio signal.
BOARD DESIGN AND LAYOUT
CONSIDERATIONS
V
CC
, V
DD
PINS
The digital and analog power supply lines to the PCM1801
should be bypassed to the corresponding ground pins with both
0.1
μ
F and 10
μ
F capacitors as close to the pins as possible to
maximize the dynamic performance of the ADC. Although
PCM1801 has two power lines to maximize the potential of
dynamic performance, using one common power supply is
LRCK
1.4V
1.4V
0.5V
DD
BCK
DOUT
t
BCKH
t
LRCP
t
CKDO
t
LRDO
t
BCKP
t
BCKL
t
LRHD
t
LRSU
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
LRCK Set Up Time to BCK Rising Edge
LRCK Hold Time to BCK Rising Edge
LRCK Period
Delay Time BCK Falling Edge to DOUT Valid
Delay Time LRCK Edge to DOUT Valid
Rising Time of All Signals
Falling Time of All Signals
t
BCKP
t
BCKH
t
BCKL
t
LRSU
t
LRHD
t
LRCP
t
CKDO
t
LRDO
t
RISE
t
FALL
300
120
120
80
40
20
–20
–20
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
40
40
20
20
NOTE: Timing measurement reference level is (V
/V
)/2. Rising and falling time is measured from 10% to
90% of I/O signals’ swing. Load capacitance of DOUT signal is 20pF.
FIGURE 5. Audio Data Interface Timing (LRCK and BCK are inputs).
recommended to avoid unexpected power supply problems,
such as latch-up due to power supply sequencing.
AGND, DGND PINS
To maximize the dynamic performance of the PCM1801,
the analog and digital grounds are not internally connected.
These points should have very low impedance to avoid
digital noise feedback into the analog ground. They should
be connected directly to each other under the PCM1801
package to reduce potential noise problems.
V
IN
PINS
A 1.0
μ
F tantalum capacitor is recommended as an AC-
coupling capacitor which establishes a 5.3Hz cut-off fre-
quency. If a higher full-scale input voltage is required, the
input voltage range can be increased by adding a series
resistor to the V
IN
pins.
V
REF
INPUTS
A 4.7
μ
F tantalum capacitor is recommended between ground
and the V
REF
1 and V
REF
2 references to ensure low source
impedance. These capacitors should be located as close as
possible to the V
REF
1 or V
REF
2 pins to reduce dynamic errors
on the ADC’s references.
SYSTEM CLOCK
The quality of the system clock can influence dynamic
performance in the PCM1801. The duty cycle, jitter, and
threshold voltage at the system clock input pin must be
carefully managed. When power is supplied to the part, the
system clock, bit clock (BCK), and word clock (LRCK)
should also be supplied simultaneously. Failure to supply
the audio clocks will result in a power dissipation increase
of up to three times normal dissipation and may degrade
long-term reliability if the maximum power dissipation limit
is exceeded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1801U | 制造商:Texas Instruments 功能描述:16BIT AUDIO ADC SMD 1801 SOIC14 制造商:Texas Instruments 功能描述:16BIT AUDIO ADC, SMD, 1801, SOIC14 制造商:Texas Instruments 功能描述:16BIT AUDIO ADC, SMD, 1801, SOIC14; Resolution (Bits):16bit; Sampling Rate:48kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Supply Current:18mA; Digital IC Case Style:SOIC; No. of Pins:14; Input ;RoHS Compliant: Yes |
| PCM1801U/2K | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 16-Bit Stereo ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| PCM1801U/2KG4 | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 16-Bit Stereo ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| PCM1801UG4 | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 16-Bit Stereo ADC RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| PCM1802 CL001 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 18AWG CLR 1000' |
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