參數(shù)資料
型號(hào): PCM1800E
英文描述: Single-Ended Analog Input 20-Bit Stereo ANALOG-TO-DIGITAL CONVERTER
中文描述: 單端模擬輸入20位立體聲模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 9/15頁(yè)
文件大小: 172K
代理商: PCM1800E
9
PCM1800
THEORY OF OPERATION
PCM1800 consists of a bandgap reference, two channels of
a single-to-differential converter, a fully differential 5th-
order delta-sigma modulator, a decimation filter (including
digital high pass), and a serial interface circuit. The Block
Diagram illustrates the total architecture of PCM1800, the
Analog Front-End diagram illustrates the architecture of the
single-to-differential converter, and the anti-aliasing filter is
illustrated in the Block Diagram. Figure 1 illustrates the
architecture of the 5th-order delta-sigma modulator and
transfer functions.
An internal high precision reference with two external ca-
pacitors provides all reference voltages which are required
by the converter, and defines the full-scale voltage range of
both channels. The internal single-to-differential voltage
converter saves the design, space and extra parts needed for
external circuitry required by many delta-sigma converters.
The internal full differential architecture provides a wide
dynamic range and excellent power supply rejection perfor-
mance.
The input signal is sampled at 64X oversampling rate,
eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a 1-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of
the audio band in the frequency domain. The high order of
the modulator enables it to randomize the modulator out-
puts, reducing idle tone levels.
The 64f
S
, 1-bit stream from the modulator is converted to
1f
S
, 20-bit digital data by the decimation filter, which also
acts as a low pass filter to remove the shaped quantization
noise. The DC components are removed by a high pass filter,
and the filtered output is converted to time-multiplexed
serial signals through a serial interface which provides
flexible serial formats and Master/Slave Modes.
SYSTEM CLOCK
The system clock for PCM1800 must be either 256f
S
, 384f
S
,
or 512f
S
, where f
S
is the audio sampling frequency. The
system clock must be supplied on SYSCLK (pin 16).
PCM1800 also has a system clock detection circuit which
automatically senses if the system clock is operating at
256f
S
, 384f
S
, or 512f
S
.
When 384f
S
and 512f
S
system clock is in Slave Mode, the
system clock is divided into 256f
S
automatically. The 256f
S
clock is used to operate the digital filter and the modulator.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies. Figure 2 illustrates the system
clock timing.
FIGURE 1. Simplified Diagram of the PCM1800 5th-Order Delta-Sigma Modulator.
FIGURE 2. System Clock Timing.
+
+
+
+
+
5th SW-CAP
Integrator
4th SW-CAP
Integrator
3rd SW-CAP
Integrator
2nd SW-CAP
Integrator
1st SW-CAP
Integrator
+
+
+
+
+
+
1-Bit
DAC
H(z)
Qn(z)
Analog In
X(z)
Digital Out
Y(z)
Y(z) = STF(z) X(z) + NTF(z) Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
Comparator
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256f
S
384f
S
512f
S
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
t
CLKIH
System Clock Pulse Width High
t
CLKIH
t
CLKIL
12ns (min)
System Clock Pulse Width Low
12ns (min)
t
CLKIL
SYSCLK
2.0V
0.8V
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