參數(shù)資料
型號(hào): PCM1800E
英文描述: Single-Ended Analog Input 20-Bit Stereo ANALOG-TO-DIGITAL CONVERTER
中文描述: 單端模擬輸入20位立體聲模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 14/15頁(yè)
文件大?。?/td> 172K
代理商: PCM1800E
14
PCM1800
SYNCHRONIZATION WITH
DIGITAL AUDIO SYSTEM
In Slave Mode, PCM1800 operates with LRCK synchro-
nized to the system clock (SYSCLK). PCM1800 does not
require a specific phase relationship between LRCK and
SYSCLK, but does require the synchronization of LRCK
and SYSCLK. If the relationship between LRCK and
SYSCLK changes more than 6 bit clocks (BCK) during one
sample period due to LRCK or SYSCLK jitter, internal
operation of the ADC halts within 1/f
S
and digital output is
forced into BPZ code until resynchronization between LRCK
and SYSCLK is completed. In case of changes less than 5 bit
clocks (BCK), resynchronization does not occur and above
digital output control and discontinuity does not occur.
ADC DATA OUTPUT AT RESET
Figures 9 and 10 illustrate the ADC digital output when the
reset operation is done and synchronization is lost. During
undefined data, it may generate some noise in the audio signal.
Also, the transition of normal to undefined data and undefined
or zero data to normal makes a discontinuity of data on the
digital output, and may generate some noise in the audio signal.
BOARD DESIGN AND LAYOUT
CONSIDERATIONS
V
CC
, V
DD
PINS
The digital and analog power supply lines to the PCM1800
should be bypassed to the corresponding ground pins with
both 0.1
μ
F ceramic and 10
μ
F tantalum capacitors as close to
the pins as possible to maximize the dynamic performance
of the ADC. Although PCM1800 has two power lines to
maximize the potential of dynamic performance, using one
common power supply is recommended to avoid unexpected
power supply problems, such as latch-up or power supply
sequence.
AGND, DGND PINS
To maximize the dynamic performance of the PCM1800,
the analog and digital grounds are not internally connected.
These points should have very low impedance to avoid
digital noise feedback into the analog ground. They should
be connected directly to each other under the parts to reduce
potential noise problems.
FIGURE 9. ADC Output for Power-On Reset and RSTB Control.
FIGURE 10. ADC Output When Synchronization is Lost and for Resynchronization.
Reset
Ready/Operation
Internal Reset
DOUT
(1)
Zero Data
Normal Data
(2)
18436/f
S
Reset Release
Power ON
RSTB ON
NOTES: (1) In the Master Mode, FSYNC, BCK, and LRCK are outputs similar to DOUT.
(2) The HPF transient response (exponentially attenuationed signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
Synchronous
Asynchronous
Synchronization
Lost
Resynchronization
1/f
S
Synchronous
Normal
Normal
(2 )
Zero Data
32/f
S
Undefined Data
State of
Synchronization
DOUT
(1 )
NOTES: (1) Applies only for Slave Mode—the loss of synchronization never occurs in Master Mode.
(2) The HPF transient response (exponentially attenuationed signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCM1800E 制造商:Texas Instruments 功能描述:20BIT AUDIO DAC SMD 1800 SSOP24 制造商:Texas Instruments 功能描述:20BIT AUDIO DAC, SMD, 1800, SSOP24 制造商:Texas Instruments 功能描述:20BIT AUDIO DAC, SMD, 1800, SSOP24; Resolution (Bits):20bit; Sampling Rate:48kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Supply Current:18mA; Digital IC Case Style:SSOP; No. of Pins:24; Input ;RoHS Compliant: Yes
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