參數(shù)資料
型號: PCM1773RGAR
元件分類: DAC
英文描述: LOW VOLTAGE AND LOW POWER STEREO AUDIO DIGITAL TO ANALOG CONVERTER WITH LINEOUT AMPIIFIER
中文描述: 低電壓和低功耗立體聲音頻數(shù)模轉(zhuǎn)換器與線路輸出AMPIIFIER
文件頁數(shù): 20/29頁
文件大小: 309K
代理商: PCM1773RGAR
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
www.ti.com
20
HARDWARE CONTROL (PCM1773)
The digital functions of the PCM1773 device are capable of hardware control. Table 3 shows selectable formats, Table 4
shows de-emphasis control, and Table 5 shows analog mixing control.
Table 3. Data Format Select
FMT
Low
High
DATA FORMAT
16- to 24-bit, left-justified format
16- to 24-bit, I2S format
Table 4. De-Emphasis Control
DEMP
Low
High
DE-EMPHASIS FUNCTION
44.1-kHz de-emphasis OFF
44.1-kHz de-emphasis ON
Table 5. Analog Mixing Control
AMIX
Low
High
ANALOG MIXING
Analog mixing OFF
Analog mixing ON
SOFTWARE CONTROL (PCM1772)
The PCM1772 device has many programmable functions that can be controlled in the software control mode. The functions
are controlled by programming the internal registers using MS, MC, and MD.
The software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial
control interface is used to program the on-chip mode registers. MD is the serial data input, used to program the mode
registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode control port select signal.
REGISTER WRITE OPERATION (PCM1772)
All write operations for the serial control port use 16-bit data words. Figure 25 shows the control data word format. The most
significant bit must be 0. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The eight
least significant bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
Figure 26 shows the functional timing diagram for writing to the serial control port. To write data into the mode register, data
is clocked into an internal shift register on the rising edge of the MC clock. Serial data can change on the falling edge of
the MC clock and must be stable on the rising edge of the MC clock. The MS signal must be low during the write mode,
and the rising edge of the MS signal must be aligned with the falling edge of the last MC clock pulse in the 16-bit frame.
The MC clock can run continuously between transactions while the MS signal is low.
MSB
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Register Index (or Address)
Register Data
Figure 25. Control Data Word Format for MD
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