參數(shù)資料
型號(hào): PCM1773RGAR
元件分類: DAC
英文描述: LOW VOLTAGE AND LOW POWER STEREO AUDIO DIGITAL TO ANALOG CONVERTER WITH LINEOUT AMPIIFIER
中文描述: 低電壓和低功耗立體聲音頻數(shù)模轉(zhuǎn)換器與線路輸出AMPIIFIER
文件頁(yè)數(shù): 16/29頁(yè)
文件大小: 309K
代理商: PCM1773RGAR
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
www.ti.com
16
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1772 and PCM1773 devices is comprised of a 3-wire synchronous serial port. It
includes terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial data present
on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1772 and PCM1773 devices on
the rising edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data into the serial audio interface
internal registers.
Both LRCK and BCK of the PCM1772 device support the slave and master modes which are set by FMT (register 3). LRCK
and BCK are outputs during the master mode and inputs during the slave mode.
In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended that LRCK
and BCK be derived from SCKI. LRCK is operated at the sampling frequency, f
S
. BCK can be operated at 32, 48, and 64
times the sampling frequency.
In master mode, BCK and LRCK are derived from the system clock, and these terminals are outputs. The BCK and LRCK
are synchronous to SCKI. LRCK is operated at the sampling frequency, f
S
. BCK can be operated at 64 times the sampling
frequency.
The PCM1772 and PCM1773 devices operate under LRCK synchronized with the system clock. The PCM1772 and
PCM1773 devices do not need a specific phase relationship between LRCK and the system clock, but do require the
synchronization of LRCK and the system clock. If the relationship between the system clock and LRCK changes more than
±
3BCK during one sample period, internal operation of the PCM1772 and PCM1773 devices halt within 1/f
S
, and the analog
output is kept in last data until resynchronization between system clock and LRCK is completed.
AUDIO DATA FORMATS AND TIMING
The PCM1772 device supports industry-standard audio data formats, including standard, I
2
S, and left justified. The
PCM1773 device supports the I
2
S and left-justified data formats. Table 2 lists the main features of the audio data interface.
Figure 22 shows the data formats. Data formats are selected using the format bits, FMT[2:0] of control register 3 in case
of the PCM1772 device, and are selected using the FMT terminal in case of the PCM1773 device. The default data format
is 24-bit, left-justified, slave mode. All formats require binary 2s complement, MSB-first audio data. Figure 23 shows a
detailed timing diagram for the serial audio interface in slave mode. Figure 24 shows a detailed timing diagram for the serial
audio interface in master mode.
Table 2. Audio Data Interface
AUDIO-DATA INTERFACE FEATURE
CHARACTERISTIC
Standard, I2S, left justified
I2S, left justified
16-, 20-, 24-bits selectable
MSB first, 2s complement
Audio data interface format
(PCM1772)
(PCM1773)
Audio data bit length
Audio data format
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