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參數(shù)資料
| 型號： | PCM1750P |
| 英文描述： | Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙通道CMOS 18位單片音頻模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 240K |
| 代理商： | PCM1750P |
PCM1750
8
occurs during the SAMPLE period (see the timing diagram
shown in Figure 2). These errors are stored on the AC
coupling capacitors (CAZ1 to CAZ4, shown in Figure 1)
between the gain stages. During the SAMPLE period the
inputs to gain stages A1 and A2 and the latch are grounded
by switches H1, H2, and AZ1 to AZ4. Capacitors CAZ1 and
CAZ2 track the amplified offset voltage of gain stage A1
and capacitors CAZ3 and CAZ4 do the same for A2. At the
beginning of a conversion cycle, the autozeroing switches
open and the instantaneous amplified value of both the DC
offset voltage and the low-frequency flicker noise is stored
on the coupling capacitors to produce zero comparator offset
during a conversion cycle.
SUCCESSIVE APPROXIMATION
CONVERSION PROCESS
The timing diagram in Figure 2 illustrates the successive
approximation routine of the PCM1750. Control signals
CONVERT and CLK are derived from a master system
clock which comes from a 256f
S
(256
X
the base sampling
frequency of 48kHz) clock used by the optional digital filter.
There are 64 clocks shown in the timing diagram because the
PCM1750 is shown operating at 4 times the standard 48kHz
sample rate (192kHz).
Several events occur on the rising edge of the CONVERT
command. Switches AZ1 to AZ4, H1 and H2 open and
switch S1 reconnects the MSB capacitor, C1, from V
IN
to
analog common (see Figure 1). This terminates the com-
parator auto-zero cycle and simultaneously switches (co-
phase sampling) both converters from tracking their respec-
tive input signals into the HOLD mode, thus capturing the
instantaneous value of V
IN
(with a small delay specified as
the aperture time).
At the start of a conversion cycle when S1 is switched to
analog common, the sampled input signal V
IN
will appear at
the comparator input as –V
IN
/2 due to the 2-to-1 capacitive
divider action of Cl = C2 + C3 + ... C18. In a somewhat
similar manner, V
REF
is transferred to the comparator input
as –V
REF
/2 to create a bipolar offset.
The 19-bit shift register, shown in Figure 4, controls testing
of the bits of the dual ADCs beginning with bit-1 (MSB) and
proceeding one bit at a time to bit-18 (LSB), leaving ON
those bits that don’t cause the cumulative value of the
CDAC to exceed the original input value and leaving OFF
those bits that do. Since the bits of both channels are tested
together, only one shift register is required to control both
ranks of 18 data latches.
For example, the testing of bit-2 proceeds in the following
manner. The positive pulse from the second shift register
element SR2, (see Figure 2 and 4) is applied to the bit-2 data
latch and NOR gate. The NOR gate in turn drives S2 and
switches bit-2 at the beginning of the bit-2 test interval. Note
that the bit interval must be long enough to allow both the
comparator input to settle and the comparator to respond. On
1
2
18
19
3
*Optional
Digital Filter
54 55 56
57 58 59 60
61 62 63 64
1
2
3
4
5
6
7
8
9
10 11 12
T1
T4
T6
T3
T5
T7
T9
REF
T
Convert
Ext Clk In
SOUT
Bit 18
LSB
Bit 1
MSB
Bit 2
Bit 17
T8
T2
PARAMETER
T1
(1 x TREF)
T2
(6 x TREF)
T3
(4 x TREF)
T4
(3 x TREF)
T5
(1 x TREF)
T6
(2 x TREF)
T7
T8
T9
TCONV (64 x TREF)
TREF (Sample Rate /64)
DESCRIPTION
Convert Command High
S/H Acquisition Time
Convert to Clock time
Master Clock Input
Clock High
Clock Low
Data Hold Time
Data Setup Time
Data Valid Time
Conversion Throughput Time
Ext Digital Filter Clock
MIN
24
420
281
211
24
45
10
NOMINAL
33
486
326
244
33
67
MAX
55
UNITS
% of T4
ns
ns
ns
% of T4
% of T4
ns
ns
ns
μ
s
ns
1302
977
55
76
100
1212
20.8
326
120
4.5
70
154
5.2
81
Note: The nominal timing shown in this diagram is all done automatically by the DF1750 digital filter. Only the
optional digital filter clock is required when the DF1750 is used.
FIGURE 3. PCM1750 Setup and Hold Timing Diagram.
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| PCM1750U | Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
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| PCM1755DBQR | 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER |
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| PCM1753DBQ | 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1750P/PCM1750U | 制造商:BB 制造商全稱:BB 功能描述:PCM1750P. PCM1750U - Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
| PCM1750U | 功能描述:音頻模/數(shù)轉換器 IC Dual CMOS 18-Bit Mono A/D Converter RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| PCM1750U/1K | 功能描述:音頻模/數(shù)轉換器 IC Dual CMOS 18-Bit Mono A/D Converter RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| PCM1750U/1KG4 | 功能描述:音頻模/數(shù)轉換器 IC Dual CMOS 18-Bit Mono A/D Converter RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| PCM1750U1K | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual CMOS 18-Bit Monolithic Audio NALOG-TO-DIGITAL CONVERTER |
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