參數(shù)資料
型號(hào): PCM1750
英文描述: Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER
中文描述: 雙通道CMOS 18位單片音頻模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 14/18頁(yè)
文件大?。?/td> 240K
代理商: PCM1750
PCM1750
14
INPUT SIGNAL CONDITIONING
RC Input Circuit
Note the 150
resistors and 220pF capacitors on each
analog input as shown in the connection diagram (Figure 7).
This input circuit configuration is required to achieve opti-
mum SNR performance of the PCM1750. Various other
component values will yield satisfactory results, but the
resistor should never exceed 200
.
Buffer Amplifier
To avoid introducing distortion, the PCM1750 input must be
driven by a low active impedance source (op amps such as
the NE5532, Burr-Brown OPA2604, or equivalent are ideal).
EXTERNAL ADJUSTMENTS
The simplified circuit diagram (see Figure 1) shows one of
two complete channels on the PCM1750. The input switched
capacitors, trim DAC and comparator are detailed. The trim
DAC switches are activated whenever the corresponding bit
is chosen during the successive approximation routine. The
first 12 bits of the ADC have corresponding trim DAC
circuits. The R1a to R12a and R1b to R12b resistors can be
laser trimmed at the wafer level if necessary to correct for
any nonlinearities. The nominal voltage for the internally
generated V
REF
is 2.75V and it is a relatively low imped-
ance, buffered voltage output. It should be noted that just
the act of connecting the optional adjustment circuits will
affect the MSB DLEs and bipolar offsets since it is unlikely
that the initial potentiometer settings (even if centered)
would match the factory trimmed null potentials. If con-
nected, the potentiometers must be properly adjusted.
MSB Adjust
The MSB adjust pin connects to the center of the R1a/R1b
resistive divider for bit-1. After laser trimming this point is
nominally 100mV. All the MSB and offset adjust pins
should be connected to ground using a 0.01
μ
F capacitor,
especially if traces to the potentiometers are long. If the
adjust pins are not used, they should still be bypassed to
ground.
Since there are internal 5k
resistors and clamp diodes to
both ground and +5V on the MSB and offset adjust pins,
there are obvious limits to their range of adjustment. With a
nominal internal voltage on these points of +100mV, there
will be a greater limitation in making negative adjustments
than positive. A negative voltage at either adjustment pin,
however, is acceptable up to one diode drop (–0.6V) below
ground.
The preferred method of MSB DLE adjustment is to input a
small level signal and adjust for minimum THD+N.
Offset Adjust
The offset adjust switch (S
OFF
) position is controlled by
whether the ADC is in the sample or hold mode. Switching
from sample to hold effectively allows any charge offsets
associated with the sampling process to be eliminated.
Grounding the input to the converter as far ahead of the A/D
as possible (in front of the anti-aliasing filter for example)
and then adjusting the bipolar zero error will remove the
offsets associated with the entire sampling system.
LAYOUT CONSIDERATIONS
Power Requirements
Noise on the power supply lines can degrade converter
performance, especially noise and spikes from a switching
power supply. Appropriate supplies or filters must be used.
Although the PCM1750 positive supplies have separate
digital and analog +5V, for most applications the +5V
digital supply pins should be connected to the +5V analog
supply. If they aren’t connected together, a potential latchup
condition can occur when the power supplies are not turned
on at the same time. If one supply pin is powered and the
other is not, the PCM1750 may latch up and draw excessive
current. In normal operation, this is not a problem because
both +V
A
and +V
D
should be connected together. However,
during evaluation, incoming inspection, repair, etc., where
the potential of a “hot” socket exists, care should be taken to
power the PCM1750 only after it has been socketed.
All supplies should be bypassed as shown in Figure 7. The
bypass capacitors should placed as close to their respective
supply pins as possible. Additional .01
μ
F capacitors may be
placed in parallel with the larger value capacitors to increase
high-frequency rejection, but generally they are not required
when high quality tantalums are used. The 0.1
μ
F capacitor
between P21 and P22 should be a low leakage type (such as
ceramic) and must be put as close to these pins as possible
to reduce noise pickup.
FIGURE 8a. Circuit for External Gain Adjustment Using the
Internal Reference.
10μF
+
18
1k
19
1/2 5532
VREF
VREF
INR
OUTR
10μF
+
25
1k
24
1/2 5532
VREF
VREF
INL
OUTL
39k
+5V
–5V
+5V
–5V
50k
50k
1μF
+
1μF
+
39k
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