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參數資料
| 型號： | PCM1750 |
| 英文描述： | Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙通道CMOS 18位單片音頻模擬數字轉換器 |
| 文件頁數： | 11/18頁 |
| 文件大小： | 240K |
| 代理商： | PCM1750 |
11
PCM1750
can be used to purposely alias a band-limited signal down
into the baseband of the converter. This technique is called
undersampling and can be used to directly down-convert an
intermediate frequency riding on a much higher carrier
frequency.
DIGITAL I/O AND TIMING
Input/Output Logic Compatibility
Digital logic on the PCM1750 is CMOS compatible. Digital
outputs on the PCM1750 are capable of driving a minimum
of two standard TTL input loads.
Digital output coding is in binary two’s complement. Table I
gives the precise input/output voltage/code relationships for
the PCM1750. Figure 5 shows these same relationships in a
graphical format.
Convert Command and External Clock Input
A conversion is initiated on its positive going edge of the
convert command. Although the convert command can re-
turn low at any time (prior to 50ns before the rising edge of
the 19th clock), a typical convert command pulse width of
81ns (as called out in Figure 3) is specified for a 192kHz
sample rate (f
S
). The reason for a pulse width spec is to
reduce problems associated with digital logic feedthrough
noise. The return of convert command to a logic low level in
the specified time interferes least with the successive ap-
proximation process. Also, it should be noted that putting
fast logic edges (<5ns) on convert command (P11) and the
external clock input (P4) may cause logic feedthrough to the
analog stages in the converter and will result in added
distortion during the sampling and conversion process.
Using the optional DF1750 digital filter provides adequately
slow transitions to maintain full specification performance.
If necessary, an external RC, on the convert command line
may be used to slow fast logic edges.
As with the convert command, the external clock input is
positive edge triggered and is not duty-cycle dependent
other than to improve digital feedthrough noise immunity. A
50% duty cycle clock can be used instead of 33% if desired.
Refer to Figure 3 for recommended timing relationships.
Regardless of what clock duty cycle is used, all operations
relating to valid data clocking should be synchronized to the
rising edge of the clock input.
Although there is a maximum conversion time called out in
the specification table, the PCM1750 can have a consider-
ably longer conversion cycle. Droop of the internal capaci-
tors will ultimately determine what the true maximum
conversion time can be. The min/typ/max times shown in
Figure 3 are based on minimum sample rate of 48kHz, a
typical of 192kHz, and a maximum of 222kHz. All specifi-
cations are tested at 192kHz. The minimum sample rate
assumption is based on clock periods that increase as time
between convert commands increases. Any sample rate
down to near DC can be utilized by observing maximum
clock cycle requirements and spacing convert commands to
achieve lower sample rates. This means that the time interval
T2 shown in Figure 3 does not have a maximum value.
Clock Lockout
Any number of clocks can be given to the PCM1750 beyond
the 19 required for normal operation. If a continuous clock
is used, all clocks beyond the 19th are gated off by the
PCM1750’s internal logic until the next positive going edge
of the convert command. The converter also goes into the
sample (track) mode starting on the positive edge of the 19th
clock until the next positive edge of the convert command,
regardless of how many additional clocks are offered. The
ideal operation of the converter stops the clock input after
the 19th during this critical signal acquisition time. This is
the timing shown in Figure 3 . The critical timing aspect that
must be observed if a clock input other than the recom-
mended is used, is that ample time following the positive
edge of convert command proceed the next rising clock
edge. If this time is shortened, the most important bit-1
(MSB) decision, which is finalized on the first clock edge
after convert command, will be adversely affected. In other
words, the clock input cannot have a rising edge during the
time interval T3 shown in Figure 3.
SIGNAL-TO-NOISE RATIO
Another specification for A/D converters is signal-to-noise
ratio (SNR). For this measurement, a full-scale 1kHz signal
is applied and the sampling rate of the PCM1750 is set at
192kHz. An FFT is performed on the digital output and the
noise power in the non-harmonic audio-bandwidth frequency
bins (20Hz to 24kHz) is summed and expressed in relation
to the full-scale input signal.
One advantage of using the PCM1750 in this oversampled
mode with the optional DF1750 digital decimation filter is
that the converter noise is spread over the full 0Hz to 96kHz
passband and then suppressed by the digital filter stopband
attenuation (from 24kHz to 96kHz). This effectively in-
creases the SNR of the PCM1750 by 6dB when it is used as
an audio bandwidth converter. The other advantage is that
the need for a higher-order anti-aliasing input filtering is
greatly reduced.
THD + N
The key specification for the PCM1750 is total harmonic
distortion plus noise (THD+N). In terms of signal measure-
ment, THD+N is the ratio of Distortion
RMS
+ Noise
RMS
/
Signal
RMS
expressed in dB. For the PCM1750, THD+N is
100% tested at all three specified input levels using the
production test setup shown in Figure 6. For this measure-
ment, as with the SNR test, a full-scale 1kHz signal is
applied and the sampling rate of the PCM1750 is set at
192kHz (which is 4X the standard digital audio sample rate
of 48kHz). An FFT is performed on the digital output and
the total power in all audio-bandwidth frequency bins (20Hz
to 24kHz) is summed and expressed in relation to the full-
scale input signal.
For the audio band, the THD+N of the PCM1750 is essen-
tially flat for all frequencies and input signal levels. In the
Typical Performance Curves
THD+N versus Frequency
相關PDF資料 |
PDF描述 |
|---|---|
| PCM1750P | Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
| PCM1750U | Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
| PCM1753DBQR | 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER |
| PCM1755DBQR | 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER |
| PCM1753 | 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCM1750P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PCM1750P/PCM1750U | 制造商:BB 制造商全稱:BB 功能描述:PCM1750P. PCM1750U - Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER |
| PCM1750U | 功能描述:音頻模/數轉換器 IC Dual CMOS 18-Bit Mono A/D Converter RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| PCM1750U/1K | 功能描述:音頻模/數轉換器 IC Dual CMOS 18-Bit Mono A/D Converter RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| PCM1750U/1KG4 | 功能描述:音頻模/數轉換器 IC Dual CMOS 18-Bit Mono A/D Converter RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
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