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參數(shù)資料
| 型號(hào)： | PCM1748KE |
| 英文描述： | 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位，96kHz采樣加強(qiáng)多層次，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 323K |
| 代理商： | PCM1748KE |
PCM1748
SBAS165
15
ANALOG OUTPUTS
The PCM1748 includes two independent output channels:
V
OUT
L and V
OUT
R. These are unbalanced outputs, each
capable of driving 3.1Vp-p typical into a 5k
AC-coupled
load. The internal output amplifiers for V
OUT
L and V
OUT
R
are biased to the DC common-mode (or bipolar zero) volt-
age, equal to V
CC
/2.
The output amplifiers include an RC continuous-time filter
that helps to reduce the out-of-band noise energy present at
the DAC outputs, due to the noise shaping characteristics of
the PCM1748’s delta-sigma DACs. The frequency response
of this filter is shown in Figure 8. By itself, this filter is not
FIGURE 8. Output Filter Frequency Response.
0.1
1
10
100
1K
10K
0
–
10
–
20
–
30
–
40
–
50
–
60
R
Frequency (kHz)
ANALOG FILTER PERFORMANCE
(100Hz-10MHz)
enough to attenuate the out-of-band noise to an acceptable
level for many applications, therefore, an external low-pass
filter is required to provide sufficient out-of-band noise
rejection. Further discussion of DAC post-filter circuits is
provided in the Applications Information section of this data
sheet.
V
COM
OUTPUT
One unbuffered common-mode voltage output pin, V
COM
(pin 10), is brought out for decoupling purposes. This pin is
nominally biased to a DC voltage level equal to
V
CC
/2.
This
pin may be used to bias external circuits. An example of
using the V
COM
pin for external biasing applications is
shown in Figure 9.
ZERO FLAGS
Zero Detect Condition
Zero Detection for each output channel is independent from
the other. If the data for a given channel remains at a “0”
level for 1024 sample periods (or LRCK clock periods), a
Zero Detect condition exists for that channel.
Zero Output Flags
Given that a Zero Detect condition exists for one or more
channels, the Zero Flag pins for those channels will be set to
a logic “1” state. There are Zero Flag pins for each channel,
ZEROL (pin 12) and ZEROR (pin 11). These pins can be used
FIGURE 9. Biasing External Circuits Using the V
COM
Pin.
R
1
R
3
R
2
C
1
C
2
V
CC
10
μ
F
(a) Using V
COM
to Bias a Single-Supply Filter Stage
(b) Using a Voltage Follower to Buffer V
COM
when Biasing Multiple Nodes
(c) Using an INA134 for DC-Coupled Output
x = L or R
10
μ
F
Filtered
Output
OPA337
2
3
1
A
V
=
–
1, where A
V
=
–
R
2
R
1
V
OUT
x
V
COM
V
COM
PCM1748
+
+
Buffered
V
COM
V
CC
V+
V
–
V
CC
+
1/2
OPA2353
10
μ
F
PCM1748
25k
25k
49.9k
1%
25k
25k
SENSE
OUT
–
IN
+IN
REF
x = L or R
10
μ
F
To Low-Pass
Filter Stage
INA134
V
OUT
x
V
COM
PCM1748
+
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| PCM1748KE/2K | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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