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參數(shù)資料
| 型號： | PCM1742E |
| 英文描述： | 24-Bit, 192kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位192kHz采樣加強多層次，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCM1742E |
PCM1742
SBAS176
9
FIGURE 3. Audio Data Input Formats.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1742 is comprised of
a 3-wire synchronous serial port. It includes LRCK (pin 3),
BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit
clock, and is used to clock the serial data present on DATA
into the audio interface’s serial shift register. Serial data is
clocked into the PCM1742 on the rising edge of BCK.
LRCK is the serial audio left/right word clock used to latch
serial data into the serial audio interface’s internal registers.
Both LRCK and BCK should be synchronous to the
system clock. Ideally, it is recommended that LRCK and
BCK be derived from the system clock input, SCK. LRCK
is operated at the sampling frequency, f
S
. BCK may be
operated at 32, 48, or 64 times the sampling frequency (I
2
S
format except BCK = 32f
S
). Internal operation of the
PCM1742 is synchronized with LRCK. Accordingly, it is
held when the sampling rate clock of LRCK is changed or
SCK and/or BCK is broken at least for one clock cycle. If
SCK, BCK, and LRCK are provided continuously after this
hold condition, the internal operation will be resynchronized
automatically, less than 3/f
S
period. In this resynchronize
period, and following 3/f
S
, analog output is forced to the
bipolar zero level, or
V
CC
/2.
External resetting is not required.
AUDIO DATA FORMATS AND TIMING
The PCM1742 supports industry-standard audio data formats,
including Standard, I
2
S, and Left-Justified, as shown in
Figure 3. Data formats are selected using the format bits,
FMT[2:0], in Control Register 20. The default data format is
24-bit left justified. All formats require Binary Two’s Comple-
ment, MSB-first audio data. See Figure 4 for a detailed timing
diagram of the serial audio interface.
1/f
S
L-Channel
R-Channel
LRCK
BCK
(= 48 or 64f
S
)
18-Bit Right-Justified
DATA
DATA
(2) I
2
S Data Format: L-Channel = LOW, R-Channel = HIGH
(3) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW
(1) Standard Data Format: L-Channel = HIGH, R-Channel = LOW
1/f
S
L-Channel
R-Channel
LRCK
BCK
(= 32, 48
or 64f
S
)
16-Bit Right-Justified, BCK = 48f
S
or 64f
S
1
2
3
N-2 N-1 N
1
2
1
2
3
N-2 N-1 N
1/f
S
L-Channel
R-Channel
LRCK
BCK
(= 32, 48 or 64f
S
)
2
1
1
2
3
N-2 N-1 N
1
2
3
N-2 N-1 N
14 15 16
16 17 18
18 19 20
14 15 16
1
2
3
DATA
22 23 24
22 23 24
1
2
3
DATA
18 19 20
1
2
3
DATA
16 17 18
1
2
3
DATA
24-Bit Right-Justified
14 15 16
1
2
3
22 23 24
1
2
3
18 19 20
1
2
3
17 18
1
2
20-Bit Right-Justified
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
14 15 16
14 15 16
1
2
3
DATA
16-Bit Right-Justified, BCK = 32f
S
14 15 16
1
2
3
LSB
MSB
LSB
MSB
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| PCM1742E/2K | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHZ Samp Enh Delta-Sig DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1742E/2KG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHZ Samp Enh Delta-Sig DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1742EG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHZ Samp Enh Delta-Sig DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1742KE | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHZ Samp Enh Delta-Sig DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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