參數(shù)資料
型號： PCM1742E
英文描述： 24-Bit, 192kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER
中文描述： 24位192kHz采樣加強多層次，Δ-Σ，音頻數(shù)字模擬轉換器
文件頁數(shù)： 11/22頁
文件大?。?/td> 322K
代理商： PCM1742E
PCM1742
SBAS176
11
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1742 includes a number of user-programmable
functions that are accessed via control registers. The regis-
ters are programmed using the Serial Control Interface that
was previously discussed in this data sheet. Table II lists the
available mode control functions, along with their reset
default conditions and associated register index.
Register Map
The mode control register map is shown in Table III. Each
register includes an index (or address) indicated by the
IDX[6:0] bits.
FUNCTION
RESET DEFAULT
CONTROL REGISTER
INDEX, IDX[6:0]
Digital Attenuation Control, 0dB to
–
63dB in 0.5dB Steps
Soft Mute Control
Oversampling Rate Control (64 or 128f
S
)
DAC Operation Control
De-Emphasis Function Control
De-Emphasis Sample Rate Selection
Audio Data Format Control
Digital Filter Roll-Off Control
Zero Flag Function Select
Output Phase Select
Zero Flag Polarity Select
0dB, No Attenuation
Mute Disabled
64f
S
Oversampling
DAC1 and DAC2 Enabled
De-Emphasis Disabled
44.1kHz
24-Bit Left Justified
Sharp Roll-Off
L-/R-Channel Independent
Normal Phase
High
16 and 17
18
18
19
19
19
20
20
22
22
22
AT1[7:0], AT2[7:0]
MUT[2:0]
OVER
DAC[2:1]
DM12
DMF[1:0]
FMT[2:0]
FLT
AZRO
DREV
ZREV
TABLE II. User-Programmable Mode Controls.
TABLE III. Mode Control Register Map.
IDX
(B8-B14)
REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
10
H
11
H
12
H
13
H
14
H
15
H
16
H
16
17
18
19
20
21
22
0
0
0
0
0
0
0
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
AT17
AT27
RSV
RSV
RSV
RSV
RSV
AT16
AT26
OVER
DMF1
RSV
RSV
RSV
AT15
AT25
RSV
DMF0
FLT
RSV
RSV
AT14
AT24
RSV
DM12
RSV
RSV
RSV
AT13
AT23
RSV
RSV
RSV
RSV
RSV
AT12
AT22
RSV
RSV
FMT2
RSV
AZRO
AT11
AT21
MUT2
DAC2
FMT1
RSV
ZREV
AT10
AT20
MUT1
DAC1
FMT0
RSV
DREV
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t
MCY
t
MCL
t
MCH
t
MHH
t
MLS
t
MLH
t
MDH
t
MDS
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time
(1)
MD Hold Time
MD Set Up Time
100
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Note (2)
20
20
15
20
NOTES: (1) MC rising edge for LSB to ML rising edge. (2)
3
256
f
S
sec (min), f
S
= Sampling Rate.
FIGURE 7. Control Interface Timing.
50% of V
DD
50% of V
DD
50% of V
DD
ML
MC
MD
t
MLS
t
MCH
t
MCY
t
MDS
t
MCH
t
MCL
t
MHH
t
MLH
LSB
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