參數(shù)資料
型號(hào): PCM1727
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE DUAL PLL TM
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器,具有可編程雙鎖相環(huán)商標(biāo)
文件頁(yè)數(shù): 13/15頁(yè)
文件大?。?/td> 220K
代理商: PCM1727
13
PCM1727
1024 system (SCKO2) clocks
Reset
Reset Removal
2.6V
2.2V
1.8V
V
CC
/V
DD
Internal Reset
SCKO2 Clock
DGND
AGND
V
DD
V
CA
V
CP
Digital
Power Supply
Analog
Power Supply
Reset
PCM1727 has both internal power-on reset circuit and the
RSTB pin (pin 10) which accepts an external forced reset by
RSTB = LOW. For internal power on reset, initialize (reset)
is done automatically at power on V
DD
>2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to V
CC
/2. Figure 13 illustrates
the timing of the internal power on reset.
PCM1727 accepts an external forced reset when RSTB = L.
When RSTB = L, the output of the DAC is invalid and the
analog outputs are forced to V
CC
/2 after internal initialization
(1024 system clocks count after RSTB = H.) Figure 14
illustrates the timing of the RSTB reset pin.
For system applications, the power-up time of the internal
PLL circuit to provide a stable system clock output, is
approximately 1024 system clocks plus a 15ms transient
time.
POWER SUPPLY
CONNECTIONS
PCM1727 has three power supply connections: digital (V
DD
),
analog (V
CA
), and PLL (V
CP
). Each connection also has a
separate ground return pin. It is acceptable to use a common
+5V power supply for all three power pins. If separate
supplies are used without a common connection, the delta
between the supplies during ramp-up time must be less than
0.3V. An application circuit to avoid a power-on latch-up
condition is shown in Figure 15.
FIGURE 14. RSTB-Pin Reset Timing.
FIGURE 15. Latch-up Prevention Circuit.
FIGURE 13. Internal Power-On Reset Timing.
1024 system (SCKO2) clocks
Reset
Reset Removal
SCKO2 Clock
Internal Reset
RSTB
50% of V
DD
t
RST(1)
NOTE: (1) t
RST
= 20ns min
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參數(shù)描述
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PCM1727E2K 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL-TO-ANALOG CONVERTER With Programmable Dual PLL