參數(shù)資料
型號(hào): PCM1727
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE DUAL PLL TM
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器,具有可編程雙鎖相環(huán)商標(biāo)
文件頁(yè)數(shù): 10/15頁(yè)
文件大?。?/td> 220K
代理商: PCM1727
10
PCM1727
Attenuation Level (ATT) can be controlled as following
Resistor set AL (R) (7:0).
AL (R) (7:0)
00h
01h
.
.
.
FEh
FFh
ATT LEVEL
dB (Mute)
–48.16dB
.
.
.
–0.07dB
0dB
REGISTER 1 (A1 = 0, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
res res res res res
A1 A0
LDR
AR7AR6AR5 AR4AR3 AR2AR1AR0
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res
res
res A1
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEMMUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a “HIGH” level on bit 0 will cause the output
to be muted (this is ramped down in the digital domain, so
no “click” is audible). Bit 1 is used to control de-emphasis.
A “LOW” level on bit 1 disables de-emphasis, while a
“HIGH” level enables de-emphasis.
Bit 2, (OPE) is used for operational control. Table V illus-
trates the features controlled by OPE.
SOFTWARE MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Forced to BPZ
(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
OPE = 1
OPE = 0
TABLE V. Operation Enable (OPE) Function.
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65, 536 cycles of BCKIN,
the output will be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
IZD = 1
IZD = 0
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Normal
Zero
(2)
Normal
TABLE VI. Infinite Zero Detection (IZD) Function.
RSTB = “HIGH”
RSTB = “LOW”
SOFTWARE
MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ
(1)
Forced to BPZ
(1)
Enabled
Enabled
Disabled
Disabled
TABLE VII. Reset (RSTB) Function.
NOTE: (1)
is disconnected from output amplifier. (2)
is connected to
output amplifier.
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1727 can be set up for input word resolu-
tions of 16, 20, or 24 bits:
Bit 4 (IW1)
Bit 3 (IW0)
Input Resolution
0
0
1
1
0
1
0
1
16-bit Data Word
20-bit Data Word
24-bit Data Word
Reserved
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1727 can be programmed for 16 different
states, as shown in Table VIII.
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
REVERSE
STEREO
MONO
TABLE VIII. Programmable Output Format.
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
res
res
res res res
A1
A0
IZD SF1 SF0 DSR1 DSR0 YES ATC LRP I
2
S
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency and infinite zero detection.
Bits 0 (I
2
S) and 1 (LRP) are used to control the input data
format. A “LOW” on bit 0 sets the format to “Normal”
(MSB-first, right-justified Japanese format) and a “HIGH”
sets the format to I
2
S (Philips serial data protocol). Bit 1
(LRP) is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is “LOW”, left channel data is assumed
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