參數(shù)資料
型號： PCM1721
廠商： Texas Instruments, Inc.
英文描述： Stereo Audio Digital-To-Analog Converter With Programmable PLL(帶可編程PLL立體聲音頻D\A轉換器)
中文描述： 立體聲音頻數(shù)字模擬轉換器（帶可編程鎖相環(huán)立體聲音頻?\\阿轉換器，具有可編程鎖相環(huán)）
文件頁數(shù)： 11/16頁
文件大?。?/td> 227K
代理商： PCM1721
11
PCM1721
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res
res
res A1
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEMMUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a “HIGH” level on bit 0 will cause the output
to be muted (this is ramped down in the digital domain, so
no “click” is audible). Bit 1 is used to control de-emphasis.
A “LOW” level on bit 1 disables de-emphasis, while a
“HIGH” level enables de-emphasis.
Bit 2, (OPE) is used for operational control. Table V illus-
trates the features controlled by OPE.
SOFTWARE MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Forced to BPZ
(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
OPE = 1
OPE = 0
TABLE V. Operation Enable (OPE) Function.
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1721 can be programmed for 16 different
states, as shown in Table VIII.
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
REVERSE
STEREO
MONO
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65, 536 cycles of BCKIN,
the output will be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
IZD = 1
IZD = 0
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Normal
Zero
(2)
Normal
TABLE VI. Infinite Zero Detection (IZD) Function.
RSTB = “HIGH”
RSTB = “LOW”
SOFTWARE
MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ
(1)
Forced to BPZ
(1)
Enabled
Enabled
Disabled
Disabled
TABLE VII. Reset (RSTB) Function.
NOTE: (1)
∑
is disconnected from output amplifier. (2)
∑
is connected to
output amplifier.
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1721 can be set up for input word resolu-
tions of 16, 20, or 24 bits:
Bit 4 (IW1)
Bit 3 (IW0)
Input Resolution
0
0
1
0
0
1
0
0
16-bit Data Word
20-bit Data Word
24-bit Data Word
Reserved
TABLE VIII. Programmable Output Format.
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
res
res
res res res
A1
A0
IZD SF1 SF0 DSR1 DSR0 SYS ATC LRP I
2
S
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency and infinite zero detection.
Bits 0 (I
2
S) and 1 (LRP) are used to control the input data
format. A “LOW” on bit 0 sets the format to “Normal”
(MSB-first, right-justified Japanese format) and a “HIGH”
sets the format to I
2
S (Philips serial data protocol). Bit 1
(LRP) is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is “LOW”, left channel data is assumed
when LRCIN is in a “HIGH” phase and right channel data
is assumed when LRCIN is in a “LOW” phase. When bit
1 is “HIGH”, the polarity assumption is reversed.
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is “HIGH”, the attenuation data loaded in program
Register 0 is used for both left and right channels. When
bit 2 is “LOW”, the attenuation data for each register is
applied separately to left and right channels.
Bit 3 (SYS) is the system clock selection. When bit 3 is
“LOW”, the system clock frequency is set to 384f
S
. When
bit 3 is “HIGH”, the system clock frequency is set to 256f
S
.
Bits 4 (DSR0) and 5 (DSR1) are used to control multiples
of the sampling rate:
DSR1
DSR0
Multiple
0
0
1
1
0
1
0
1
Normal
Double
One-half
Reserved
32/44.1/48kHz
64/88.2/96kHz
16/22.05/24kHz
Not Defined
相關PDF資料
PDF描述
PCM1723 Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE PLL
PCM1725 Stereo Audio DIGITAL-TO-ANALOG CONVERTER 16 Bits, 96kHz Sampling
PCM1725U Stereo Audio DIGITAL-TO-ANALOG CONVERTER 16 Bits, 96kHz Sampling
PCM1727 Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE DUAL PLL TM
PCM1728 24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER
相關代理商/技術參數(shù)
參數(shù)描述
PCM1723 制造商:BB 制造商全稱:BB 功能描述:Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE PLL
PCM1723E 功能描述:音頻數(shù)/模轉換器 IC Ster DAC w/Prog PLL RoHS:否 制造商:Texas Instruments 轉換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1723E/2K 功能描述:音頻數(shù)/模轉換器 IC Ster DAC w/Prog PLL RoHS:否 制造商:Texas Instruments 轉換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1723E/2KG4 功能描述:音頻數(shù)/模轉換器 IC Ster DAC w/Prog PLL RoHS:否 制造商:Texas Instruments 轉換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1723EG 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*