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參數(shù)資料
| 型號： | PCM1720 |
| 英文描述： | Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE |
| 中文描述： | 立體聲音頻數(shù)字模擬轉(zhuǎn)換器MPEG2/AC-3兼容 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 194K |
| 代理商： | PCM1720 |
PCM1720
8
MAPPING OF PROGRAM REGISTERS
ATTENUATION DATA LOAD CONTROL, LCH
Bit 8 (LDL) is used to simultaneously set analog outputs of
Lch and Rch. An output level is controlled by AL[0:7]
attenuation data when this bit is set to 1. When set to 0, an
output level is not controlled and remains at the previous
attenuation level. A LDR bit in Register 1 has an equivalent
function as the LDL. When one of LDL or LDR is set to 1,
the output level of the left and right channel is simulta-
neously controlled. The attenuation level is given by:
ATT = 20 log (y/256) (dB), where y = x, when
0 ≤
x
≤
254
y = x + 1, when x = 255
X is the user-determined step number, an integer value
between 0 and 255.
Example:
let x = 255
255
+
1
256
let x = 254
let x = 1
let x = 0
REGISTER 1 (A1 = 0, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
res res res res res
A1 A0
LDR
AR7AR6AR5 AR4AR3 AR2AR1AR0
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 0
res
res
res
res
res
A1
A0
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
REGISTER 1
res
res
res
res
res
A1
A0
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
REGISTER 2
res
res
res
res
res
A1
A0
PL3
PL2
PL1
PL0
IW1
IW0
OPE
DEM
MUT
REGISTER 3
res
res
res
res
res
A1
A0
IZD
SF1
SF0
res
res
res
ATC
LRP
I
2
S
PROGRAM REGISTER BIT MAPPING
PCM1720’s special functions are controlled using four pro-
gram registers which are 16 bits long. These registers are all
loaded using MD. After the 16 data bits are clocked in, ML
is used to latch in the data to the appropriate register. Table
III shows the complete mapping of the four registers and
Figure 6 illustrates the data input timing.
ATT
=
20log
0dB
ATT
=
20log
254
256
–0.068dB
ATT
=
20log
1
256
–48.16dB
ATT
=
20log
0
256
–
∞
REGISTER 0 (A1 = 0, A0 = 0)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res res
res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
REGISTER
NAME
BIT
NAME
DESCRIPTION
Register 0
AL (7:0)
LDL
A (1:0)
res
DAC Attenuation Data for Lch
Attenuation Data Load Control for Lch
Register Address
Reserved
Register 1
AR (7:0)
LDL
A (1:0)
res
DAC Attentuation Data for Rch
Attenuation Data Load Control for Rch
Register Address
Reserved
Register 2
MUT
DEM
OPE
IW (1:0)
PL (3:0)
A (1:0)
res
Left and Right DACs Soft Mute Control
De-emphasis Control
Left and Right DACs Operation Control
Input Audio Data Bit Select
Output Mode Select
Register Address
Reserved
Register 3
I
2
S
LRP
ATC
SYS
SF (1:0)
IZD
A (1:0)
res
Audio Data Format Select
Polarity of LRCIN (pin 7) Select
Attenuator Control
System Clock Select
Sampling Rate Select
Infinite Zero Detection Circuit Control
Register Address
Reserved
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
ATT = [20 log10 (ATT_DATA/255)] dB
TABLE III. Internal Register Mapping.
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