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參數(shù)資料
| 型號： | PCM1710 |
| 英文描述： | Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 立體聲音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 192K |
| 代理商： | PCM1710 |
15
PCM1710U
1.0
0.5
0
–0.5
–1.0
d
20
Frequency (Hz)
100
1k
10k
24k
SIMULATED ANALOG FILTER
FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
APPLICATION
CONSIDERATIONS
16-BIT vs 20-BIT OPERATION
In the serial mode, PCM1710 can be configured to accept
either 16-bit or 20-bit data. The specifications listed in this
data sheet are the 16-bit data. Some improvements in
dynamic performance can be realized by using 20-bit data.
Internally, the PCM1710’s digital filter uses only 20-bit
data. If the input data is 16-bit, the filter adds four zeros
to complete the 20-bit input word. Typical performance
differences between 16-bit and 20-bit data are shown in
Tables X and XI.
DATA
256fs
384fs
16-bit
20-bit
–91dB
–94dB
–93dB
–96dB
TABLE X. THD+N Performance at Full Scale.
DATA
256fs
384fs
16-bit
20-bit
94dB
96dB
96dB
98dB
TABLE XI. Dynamic Range.
DELAY TIME
There is a finite delay time in delta-sigma converters. In
A/D converters, this is commonly referred to as latency.
For a delta-sigma D/A converter, delay time is determined
by the order number of the FIR filter stage, and the chosen
sampling rate. The following equation expresses the delay
time of PCM1710:
T
D
= 22.625 x 1/fs
For f
S
= 44.1kHz, T
D
= 22.625/44.1kHz = 513.04
μ
s
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some profes-
sional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
INTERNAL RESET
If the sample rate clock (LRCIN) is stopped during opera-
tion, the infinite zero detect circuit will cause the output to
go to V
CC
/2 after 65,536 cycles of the bit clock (BCKIN).
Once a new system clock has been applied, there will be a
delay until output data is correlated to the input. This is
due to the digital delay of the filter.
When power is first applied to PCM1710, an automatic
reset function occurs after 64 cycles of LRCIN.
CHANGING SAMPLING RATE
For normal operation, LRCIN and XTI should be synchro-
nized at either 256fs or 384fs. When the sampling rate is
changed during operation, output data is invalid during the
delay period (T
D
) and for two subsequent cycles of LRCIN.
After two cycles of LRCIN, the output is a valid represen-
tation of the input data.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1710 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 15. The higher frequency rolloff
of the filter is shown in Figure 16. If the user’s application
has the PCM1710 driving a wideband amplifier, it is recom-
mended to use an external low pass filter. A simple 3rd-
order filter is shown in Figure 17. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
FIGURE 15. Low Pass Filter Frequency Response.
FIGURE 16. Low Pass Filter Frequency Response.
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
d
SIMULATED ANALOG FILTER
FREQUENCY RESPONSE
(10Hz~10MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCM1710U | Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM1712 | DIGITAL-TO-ANALOG CONVERTER |
| PCM1712U | DIGITAL-TO-ANALOG CONVERTER |
| PCM1715 | Dual Voltage Output CMOS Delta-Sigma DIGITAL-TO-ANALOG CONVERTER With On-Chip Digital Filter |
| PCM1715U | Dual Voltage Output CMOS Delta-Sigma DIGITAL-TO-ANALOG CONVERTER With On-Chip Digital Filter |
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