參數(shù)資料
型號(hào)： PCM1604
英文描述： 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
中文描述： 24位192kHz采樣,6 -通道，增強(qiáng)的多級(jí)，Δ-Σ數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 11/32頁
文件大?。?/td> 263K
代理商： PCM1604
11
PCM1604, PCM1605
FIGURE 1. System Clock Input Timing.
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1604 and PCM1605 require a system clock for
operating the digital interpolation filters and multi-level
delta-sigma modulators. The system clock is applied at the
SCKI input (pin 38). Table I shows examples of system
clock frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1604 system clock source.
To obtain optimal dynamic performance when operating
with a 192kHz sampling frequency, it is recommended that
only two channels be enabled for operation (V
OUT
1 and
V
OUT
2). The remaining four channels should be disabled by
setting bits DAC3 through DAC6 of control register 8 to
logic 1 state.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the SCKO output (pin 39). SCKO can operate at either full
(f
SCKI
) or half (f
SCKI
/2) rate. The SCKO output frequency
may be programmed using the CLKD bit of Control Regis-
ter 9. The SCKO output pin can also be enabled or disabled
using the CLKE bit of Control Register 9. The default is
SCKO enabled.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1604 includes a power-on reset function. Figure 2
shows the operation of this function.
The system clock input at SCKI should be active for at least
one clock period prior to V
DD
= 2.0V. With the system clock
active and V
DD
> 2.0V, the power-on reset function will be
enabled. The initialization sequence requires 1024 system
clocks from the time V
DD
> 2.0V. After the initialization
period, the PCM1604 will be set to its reset default state, as
described in the Mode Control Register section of this data
sheet.
The PCM1604 also includes an external reset capability
using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1604 to
initialize to its reset default state. For normal operation, RST
should be set to a logic ‘1’.
Figure 3 shows the external reset operation and timing. The
RST pin is set to logic ‘0’ for a minimum of 20ns. The RST
pin is then set to a logic ‘1’ state, which starts the initializa-
tion sequence, which lasts for 1024 system clock periods.
After the initialization sequence is completed, the PCM1604
will be set to its reset default state, as described in the Mode
Control Registers section of this data sheet.
The external reset is especially useful in applications where
there is a delay between PCM1604 power up and system
clock activation. In this case, the RST pin should be held at
a logic ‘0’ level until the system clock has been
activated.
t
SCKIH
t
SCKIH
f
SCKI
System Clock Pulse Width High t
SCKIH
System Clock Pulse Width Low t
SCKIL
: 7ns min
: 7ns min
2.0V
0.8V
“H”
“L”
SCKI
SAMPLING FREQUENCY
(f
S
)
128f
S
192f
S
256f
S
384f
S
512f
S
768f
S
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192
—
—
—
—
—
—
—
—
—
—
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
See Note 2
See Note 2
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
See Note 2
See Note 2
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
See Note 2
See Note 2
12.2880
24.5760
33.8688
36.8640
See Note 1
See Note 1
See Note 2
See Note 2
12.2880
22.5792
24.5760
18.4320
33.8688
36.8640
NOTE: (1) The 768f
S
system clock rate is not supported for f
S
> 64kHz. (2) This system clock rate is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
SYSTEM CLOCK FREQUENCY (f
SCKI
)
(MHz)
相關(guān)PDF資料
PDF描述
PCM1604Y 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
PCM1605Y 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
PCM1702 BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER
PCM1702-J BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER
PCM1702-K BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCM1604PT 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
PCM1604PTG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
PCM1604PTR 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1604PTRG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1604Y 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24Bit/192kHz Smplg 6Ch Enh Mltl D-S DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*