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參數(shù)資料
| 型號： | PCK857 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 50-150MHz differential 1:10 SDRAM clock driver(50-150MHz 差分 1:10 SDRAM 時鐘驅(qū)動器) |
| 中文描述： | 50 - 150MHz的差分1:10 SDRAM時鐘驅(qū)動器（50 - 150MHz的差分1:10 SDRAM的時鐘驅(qū)動器） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 72K |
| 代理商： | PCK857 |
Philips Semiconductors
Product specification
PCK857
50–150 MHz differential 1:10 SDRAM clock driver
2000 June 15
5
ABSOLUTE MAXIMUM RATINGS
1,2
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
MIN
MAX
V
CC
/AV
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
θ
JA
Supply voltage range
–0.5
4.6
V
Input voltage
Note 2
–0.5
V
DDQ
+ 0.5
V
DDQ
+ 0.5
±
50
±
50
±
50
V
Output voltage
Note 2
–0.5
V
Input diode current
V
I
< O or V
I
> V
CC
V
O
< O or V
O
> V
CC
V
O
= O to V
CC
mA
Output diode current
mA
Output source or sink current
mA
Storage temperature range
–65
+150
°
C
Package thermal impedance
Note 3
89
°
C/W
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under ”recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD51.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
MIN
TYP
MAX
V
CC
AV
CC
V
IL
V
IH
V
I
I
OH
I
OL
Supply voltage
2.3
2.5
2.7
V
Analog supply voltage
3.0
3.3
3.6
V
G input
0.3 XV
CC
V
G input
0.7 XV
CC
–0.3
V
CLK, FB
IN
High-level output current
V
CC
+ 0.3
–12
V
mA
Low-level output current
12
mA
timing requirements over recommended ranges or supply voltage and operating free-air temperature
PARAMETER
CONDITIONS
MIN
MAX
UNIT
f
C
Clock frequency
66
167
MHz
Input clock duty cycle
Stabilization time
1
40%
60%
0.1
mA
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics are not applicable. This parameter does not apply for input
modulation under SSC application.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK857DG | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK NPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DGG | 制造商:NXP Semiconductors 功能描述:TEN DISTRIBUTED-OUTPUT CLOCK DRIVER, 48 Pin, Plastic, TSSOP |
| PCK857DGG,512 | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK INPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DGG,518 | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK INPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DG-T | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK NPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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