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參數(shù)資料
| 型號： | PCK857 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 50-150MHz differential 1:10 SDRAM clock driver(50-150MHz 差分 1:10 SDRAM 時鐘驅(qū)動器) |
| 中文描述： | 50 - 150MHz的差分1:10 SDRAM時鐘驅(qū)動器（50 - 150MHz的差分1:10 SDRAM的時鐘驅(qū)動器） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 72K |
| 代理商： | PCK857 |
Philips Semiconductors
Product specification
PCK857
50–150 MHz differential 1:10 SDRAM clock driver
2000 June 15
3
PIN DESCRIPTION
PINS
SYMBOL
I/O
DESCRIPTION
17
AGND
Ground
Analog ground. AGND provides the ground reference for the analog
circuitry.
16
AV
CC
Power
Analog power supply. AV
CC
provides the power reference for the analog
circuitry. In addition, AV
CC
can be used to bypass the PLL for test
purposes. When AV
is strapped to ground, PLL is bypassed and CLK
is buffered directly to the device outputs. During disable (G = 0), the
PLL is powered down.
13, 14
CLK, CLK
I
Clock input. CLK provides the clock signal to be distributed by the
PCK857 clock driver. CLK is used to provide the reference signal to the
integrated PLL that generates the clock output signals. CLK must have
a fixed frequency and fixed phase for the PLL to obtain phase lock.
Once the circuit is powered up and a valid CLK is applied, a stabilization
time is required for the PLL to phase lock the feedback signal to its
reference signal.
36, 35
FB
IN
, FB
IN
I
Feedback input. FB
IN
provides the feedback signal to the internal PLL.
FB
IN
must be hard-wired to FB
OUT
to complete the PLL. The integrated
PLL synchronizes CLK and FB
IN
so that there is nominally zero phase
error between CLK and FB
IN
.
Feedback output. FB
is dedicated for external feedback. It switches
at the same frequency as CLK. When externally wired to FB
IN
, FB
OUT
completes the feedback loop of the PLL.
32, 33
FB
OUT
, FB
OUT
O
37
G
I
Output bank enable. G is the output enable for outputs Y and Y. When
G is low outputs Y are disabled to a high-impedance state. When G is
high, all outputs Y are enabled and switch at the same frequency as
CLK.
1, 7, 8, 18, 24, 25, 31, 41,
42, 48
GND
Ground
Ground
4, 11, 12, 15, 21, 28, 34,
38, 45
V
CC
Power
Power supply
3, 5, 10, 20, 22, 46, 44, 39,
29, 27
Y0, Y1, Y2, Y3, Y4, Y5,
Y6, Y7, Y8, Y9
O
Clock outputs. These outputs provide low-skew copies of CLK.
2, 6, 9, 19, 23, 47, 43, 40,
30, 26
Y0, Y1, Y2, Y3, Y4, Y5,
Y6, Y7, Y8, Y9
O
Clock outputs. These outputs provide low-skew copies of CLK.
FUNCTION TABLE
INPUTS
OUTPUTS
PLL ON/OFF
G
CLK
CLK
Y
Y
FBOUT
Z
1
Z
1
FBOUT
Z
1
Z
1
L
L
H
Z
Z
OFF
L
H
L
Z
Z
OFF
H
L
H
L
H
L
H
ON
H
X
2
H
L
H
L
H
Z
1
L
Z
1
ON
<
20 MHz
<
20 MHz
Z
Z
OFF
NOTES:
H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
1. Subject to change. May cause conflict with FBIN pins.
2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK857DG | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK NPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DGG | 制造商:NXP Semiconductors 功能描述:TEN DISTRIBUTED-OUTPUT CLOCK DRIVER, 48 Pin, Plastic, TSSOP |
| PCK857DGG,512 | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK INPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DGG,518 | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK INPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK857DG-T | 功能描述:鎖相環(huán) - PLL 1:10 SDRAM CLK NPUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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